Sage II - Pattern 2

SAGE
rr sERVrcE
MANUAL
[1.0]
CYCLER
TEST
DISK
STRAP
TEST
XI"O8
DISK STRAP
TBST
:
on
intttalizatl-on, 1f cYcLER
determlnes
that
there
are two disk drlves
It4:
and
lt5;
to be
tested,
a
quick
check
is
made
to determine
tf the
strapplng
optlons of the
floppy drlves
were set
rlght. If
incorrect,
the system may confuse
the
two drives
or
think
that there
are two drlves
when
really
tt ls only equipped
with
oner The STRAP
test wrlles 4's
to
drlve
lt4z
and wrl-tes
5's
to
drlve ll5z.
Then
1t
reads the
drl-ves,
checklng
that
the data comlng
back
matches
the
drive
nr-rmber. A,D error
shr:ws
tncorrect
strapping
or
a
drlve
that
ls not
worklng at all.
XI"O9
SHITCH
TEST :
fhe swltch
test reads the
two
groups
of dip
switches
on the back
panel
and dlsplays
their
posltlon
as
tt,rptt
or
rrdwnrt.
Each switch must
be
manually
changed
and
a key typed
to cause
the
new
posltlon
to be
read.
If
a
system
wtl1 not automatically
boot
to the devlce
speclfled, boot
to
the Eest dlskette using
elther
rrIFOrr
or
rfIFltr
and
run
thls test to
see
that the swltches
work. T'he APPENDIX
in the user manual deflnes
the
meanl-ng
of the swltches.
Note that GROUP
B swltches can
be
user deftned
lf
the IEEE-488 bus
lmplementation
is not
needed.
XI. lO
ATTACN TEST
:
The
attach
test checks
the
timing
hardware
registers
ln
lJ7 4
an
8253
and
the bios
lnterrupt
structure
for lt. A.5 second
tlmeout ls setup
wlth
the
Sage II
ATTACIT
command
to the
f
irst timed event.
A loop
ln
the mal-n
llne
of the
program
l-ncrements
a counter.
Wtren
.5
seconds ls up
r
the
ATTACHED
process
TIMER saves
the status
of
the
counter.
The saved
value
of
the
counter
shoul-d be 453
if the
event
was tfuned
properly.
Problerns
wlth the
clock,
U71,
U75,
or
lJ74
could
cause
the
ATTACH
test to
fall.
If
lt
faL1s,
the
test may
not continue
properly
and the system
must be
re-booted.
XI. I I
R.EAL
TII{E
TEST :
The
system tlmer registers
ln
lJV4
and
U75
are
checked
using the
Pascal
TII"IE( HIGH,
LOI^I)
rout
l-ne
.
The
tlme
ls saved bef ore
the RAI"ITEST
and
checked
once the RAMTEST
ls done.
The
lnterval
actually
measured
ls
Just
the length of time taken to
do
the RAI"ITEST. The
length of
the
RAI"ITEST
will
be
deternlned
by the
amount of
RAI-{
in the
system.
Each
bank
(128K)
of RAM takes about
I14
clock
tlcks to
test. A
clock
tlck
ls
1/6Ottr
of a
second. A
4
tick varl-ance
is allowedr so
that
the clock
ls
tested Lo
withln
+-
.0664
seconds.
This allowance
ls necessary
for
Ehe
refresh time,
Probl"ems
wlth the
clock, U71
,
V7 5
or
U7 4
can
cause
the
TIME
test
to
faL1.
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