Sage II - Page 5 of Schematic Diagrams; Floppy Disk Controller

SAGE II SERVICE
KIT
CPTI
BOARD CIRCUIT
DESCRIPTIONS
PAGE I
0F
SCHEMATIC
(cont)
edge
trlggered
f11p-f1op. After
reset
the
a
of
the
fltp-f1op
U51-5
whlch
ls BRD-
ls low and
the output
of
the
74LS00
U45-8
le
hlgh. The
output
of the
l.nvertlng
buffer IJ72-B
1s low and
thus the
read only
memory
chlps
U17
and
U18
are
enabled.
BRD- also
goes
to
pln
I
of
Ul4
on
page
3
and dlsables
the
RAM.
The effect
of
this circuit
is
to make
the
ROM appear
to
be
located
at address
0,
which
ls normally
the beglnnlng
of
the
RAM
address. On the
flrst occurrence
of
an
address
to the
normal
ROM locatlon ROF{-
will
go
low and
the
transparent
boot
fllp-flop
will be
preset
Q=hlgh.
1'llth BRD-
htgh, ROI'{- selects
the ROM's
ln the
normal
mode
and
the
RAI'I
+ clrcult
of
page
3
is enabled
so
that RAM
ls
agaln
addressable.
READ
I
ITRITE
The data
transfer acknowledge
signal
(
DTACK-
)
is
necessary
for the
completlon
of any
read or
write cycle
by the
processor.
Normally,
DTACK-
ls
generated
whenever
any address
in the Sage II memory
map
ls
decoded.
The
DTACK-
generation
clrcuit
consists
malnly
of
U54,
an
8
bit
parallel
out
serial shlft
register, and the
NAND
gates
U52
and
U53.
CPU boards
C80002
and
later also lnclude
tJ7
6.
This circuit
is
f
ound
ln
the upper
rtght
quadrant
of
schematic
page
1.
The
function of
thls circuit
ls to
tell
the
processor
that
the data
lines
have
had
enough
time to settle
after
a
perlpheral
device
has
been
addressecl,
and
that the
read or write
cycle
can be completed.
Thls
ls accompllshed
by taking
the logical AND
of the decoded select
llne
for
a
devlce
or
group
of devlces
and a
tlme
delay
slgnal whlch
ls approprlate
to the access
speed of the device.
llhen
upper data
strobe
(
UDS-
)
and lower data
strobe
(
LDS-)
are
lnactive
(
hlgh
),
then the output
of
U45-11
which
is a
74LS00
NAND
gate
is
1ow . A11 of
the
a
outputs of
the
7
4LSI64
shift
register
U54
are
held
low
by
clear
at
pin
9.
When
UDS-
or LDS-
go
active low
the
clear
at
pln
9
of
U54
goes
high
and
the
shtft
register
ls enabled.
Provtded
that the
refresh slgnal RF-
is l-nactlve
hlgh the
shlft register
w111
be clocked
by DSMhz-"
T'hls
ls
8
Mhz-
delayed
through
two
74LS04
lnvertlng
buffers
U37.
The
QA
output
U54-3
is the
f lrst
to
go
hlgh. Tttis
output
generates
DTACK-
at
U52-8
when
RAI'I+
is actlve
hlgh at
pin
10
and bus
error
BE- i-s
lnacEive high
at
pin
9.
DTACK-
generated from
QA
allows
the
processor
to complete
a
cycle
with no wait states.
The
QA
output
ls
also
used
ln
conJunctlon
with the buffered
read
/
write llnes BRW- and
BRI^I+ to
generate
WR-
and RD- slgnals
at
the two
74LS00
NAND
gates
U45
pi.ns
1
th"rough
6.
Output
QB
of
the shlft
register and I/O+ are comblned
at NAND
gate
U53
pI-ns
lr2rand 3
to
produce
DTACK-
when
input
/
output
devices
atre addressed
with cycle completion
after
I
wait
state.
DTACK-
ls
generated
at
U53-6
fron
QD
wlth
3
waiE states
when ROM locations are
addressed causing
U45-8
to be high. The
QC
output
at
pin
5
of
U54
would
produce
a DTACK- for a
2
wait state cycle.
57