Sage II - Parity Circuit

SAGE
rr
SERVTCE
MANUAL
[1.0J
CPU BOARD
CIRCUIT
DESCRIPTIONS
PACE
I 0F SCHEMATIC
(cont)
PB.OCESSOR
LIGHT
EI.II{ITING
DIODE
INDICATOR
The
processor
LED driver
clrcult
ts
comprlsed
of
Rl
and
2, Cl,
and
three
gates
of
U55'
a
7406
Hex inverter
buffer
with
open
collector
outputs.
The
LED ls on
whenever
the
computer
ls
powered.
The
buffer,
U65
plns
ll
and
10, drives
the
green
dlrection
of the
LED
wlth
pln
l0
low
whenever
plns
6
and
8
are
both
inactive
and
pulled
hlgh
by
Rl. I.ltren
pln
6
or
pln
8
are
active,
Pln
11
ls
low
and
pin
10
ls
pu1-led
hlgh
by
M.
Wtren
thls
side
of
the
LED
ls
htgh
the
red
dlode ls
on and
when
the
slde
toward
Rl
ls htgh
the
green
dlode ls
oD.
Cl
provldes
lntegratlon
on
the
red
slde
such
that
when
the
clrcuit
ls
belng
drlven
by
AS- f rom
an actl-ve
processor
the
LED
wtll
appear
green.
Pin
5
of
U65
is
LEDR+
whtch
orlglnates
at
U39-17
on
page
6
of schematics.
Thls
slgnal
can
be
controlled
by
software
to
set
or toggle
the
LED
to
green.
If
LEDR+
ls
Lnactlve
then
the
LED
will
be
green
only
when
the
processor
is
busy
executLng
lnstructl-ons
.
INTERRI'PT
DECODBR
Integrated
clrcult
U35 ls a
74LSl4B
decoder.
Ihe
outputs
are
plns
(,
,
7
,
the
actlve
low lnterrupt
lnputs
to
lines
go
low
the lnterruptlng
device
these
llnes
wtll
be servlced.
PR.OCESSIilG
STATES
and ls
the lnterrupt
prlortty
l.evel
and
9.
IPLO-,
IPLI-,
and
IpL2- are
the
processor
and
when
any
of these
whose
rrprlorLty
addresstt
appears
on
The
processor
outputs
at
pln
26 FCz,
pln
27
FCl, and
ptn
28
FCQ
are
the
code for
the
processlng
state
reference
classiflcation.
See the
Motorola
MC68000
Users Manual
sectLon
5
for
a
detalled
explanatlon
of
the function
of these
plns.
V27 looks
at these
llnes in
this
system
to
generate
VPA-
valld
perlpheral
address.
Ttre
7
4LSO4
buf
fer
Ul
pins
3
and
4
along
with
7
4LSL2
V52
plns
I
,
Z,
12
,
and
13
generate
a
bus
error
lf
system
T/O is trespassed
by user
and
the
supervLsor
btt ls
not
set.
RESET
The
reset
clrcult
ls
located
at the
lower
rlght
corner
of
page
I of
the
schematlcs.
Wtren
the reset
swltch
ls
closed,
pln
I of
U4 ls held
low.
pln
2
ls htgh
and thus
tJl-z,
U65-4, and
V(rs-Z
are
all
low.
In this
conditlon
HALT- and
RESET-
are
both actlve
at the
processor
and
the
transparent
boot fllpflop
U51-l
ls
cleared. I,lhen
the
swltch
ls
released
the
58 uf
capacltor
at
U4-1 beglns
to
charge.
At some
posltive
voltage
U4,
whlch ls
a
74LSl4 Schmitt trlgger,
will
toggle.
RESET-
and
HALT-
both
go
inactlve
and
the
processor
beglns execution
at
address
location
0.
The transparent
boot
clrcul-t
conslsts
of
U5l
plns
l-6 and
U45
plns
B-10.
During reset
a
low
at
U5t-l
clears
U5l whlch
ls a
74L574 D-type
positlve
56