Sage II - Modem or Serial Printer Port; Parallel Printer Port; IEEE 488

SAGE II
SERVICE KIT
CPU
BOARD
CIRCUIT
DESCRIPTIONS
PAGE
2
OF SCHEMATIC
DIAGRAMS
XVItr.Oz
PAGE
2
OF
SCHB}IATIC
DIAGRAI{S
:
Page
2 contains
system
ctrock
generation,
baud
rate generation,
an
lntel1-lgent
i.nterrupt
controller
r
8t
I/O
port
f
or the
f
loppy
drlve
controller
and
Ehe
DIP
switches,
address
decoding,
and buffers.
sYsTEI,{
CTOCK
U66
is an
tntegraLed
crystal
osc
j.llator
clrcult.
The
l6
llhz
output
at
U66-8
ls
divtded
by
U69,
a
74LS390
dual
decade
counter,
to
produce
the
I
FIttZ+
system
e.lock at
U69
pin
3.
The output
at
U69-13
ls
the
4
I'{hz*
clock"
Two
sectlons
of
U69
and
one
of
U()7 dlvide
8 Mhz*
to
produce
64
KHZ+ at
U67'9. The
4 Mf{Z+
ls
used
by the
IEEE
488
IIO
port
on
page
6
and ls
the
l-nput
at
pin
2
ro
U70
a
74LS161.
U70
ls a
synchronous
4 bit
blnary
counter"
The
output
QA
at
pin
14
is
2
MIIZ which
clocks
the
serial
ports
of
page
6.
500
KHZ
is
output
at
QC
pin
12
and
thi.s
clock
is
used
hy
the
bus
error
timeout
circuit and
to
generate
WCK+
at the
RIPPLE
CARRY
0UTPUT
pln
1-5. MFM+ is
received
at
pln
6
from
the
floppy
disk
clrcult
page
5.
The
RtrPPLE
CARRY
OUTPUT
is
lnverred
by
V72
74LS00
and
lnput
at
pin
9
to
L0AD the
counter f rom
plns
3
14 15 rand
6
to
begln
the next
count
cycle.
MFIVI+
at
pln
6
determlnes
whether
the
clock WCK+
ts at
a
250
l(hz or
500
khz rate.
Refer
ro
the floppy
disk
circuir
descrlptlon
for
more
detal1
of operatlon.
U71
is
also
a 4 bit
synchronous
binary
counter
which
can be
preset,
and is used
ln
a slurllar
conflguratlon
to
U70.
The
para1le1
input plns
3r415rand
6
preset
the
count
to
start
the
cycle
over agaln
when
the lnverted
RIPPLE
CARRY
OUT
ls applted
to
LOAD* The
ourput
QD
ar
pln
ll
is
dl5.3g KHz
,
ADDRESS
DECODING
Address
decoding
for
Ehe
ROM
and
I/O
locatlons
are
accompllshed
by three
3-lnput
NOR gates,
three
inverters,
and
two
4-lnput NAND
gates.
tJ25
is
a
7
t+L527
,
U33 a
7
4L504,
and
1124 a
7 4LS2O. These
gates
decode
Al4-
through
A23-
to
generate
the
active
low
signal-
at
U24-8 which
is
ROM-,
and at
lJZl+-6
actlve
low
signal
T/O-
is decoded
and
becomes
actlve
high
T/
M
at lnverter
U33-8.
The indivldual
chip
select
slgnals
are
generated
by
decoding
address
1lnes
A4- through
A13-
and
FC2+,
whlch
is
a
reference
class
functlon
code or-rtput
(user/supervisor)
from
the
processor,
and
then gating
wlth
the
t/O
actlve
low
slgnal
which
1s
decoded
from
A14-
through
A23-.
firLs
is
acconpllshed
by
Ul4
a
74LS2l 4-
input
AND,
\127 a
7|LSZA
4-lnput
NAND,
U19 a
74LS138
3
ro
8
llne
decoder,
and
\J&7 a
74LS139
2 to
l+
line
decoder.
This
clrcult
completely
decodes
A4*
through
A23-
so
that
the read
only
memory or
input
/
output
devlces
are
never
accessed
by tmaging"
59