Sage II - Page 4 of Schematic Diagrams; RAM Address Location; RAM Control Signals

sAcE
rr
sERvrcE
MANUAL
[1.0]
CPU
BOARD CIRCUIT
DESCRIPTIONS
XVII
CPU
BOARD CIRCUIT
DESCRIPTIONS
:
This sectlon
ls a
descrlption
of the clrcults
on
the SAGE II
board.
References
to
components
on
the
circuit
board
are
glven
as
tr1;tr
followed
by
a
number.
A description
of
the slgnal
names used
ls
glven
at
the end
of
this sectlon.
XVII.OI
PAGE I
OF SCHEMATIC
:
r{c68000
PRocBssoR
U68
is the MC68000 microprocessor
which is the
heart of the SAGE
II
MC68000 User's
I'lanual
for
a
microcomputer.
Refer
to the
Motorola
detalled
description of
this
processor.
23
address lines are
brought
out of
the
processor
and
buffered by U16,
26,
and
35.
These
are
74L5240
lnverted
tri-state
1lne
drlver/recelvers.
They
are hard selected as drlvers
only.
The output
side whlch
connects
to
J1
and other
parts
of the system
is never
in the
high impedance
state.
The
16
data
lines are
buffered
through U55
and
U43
which are
74L5245
bl-
dlrectlonal
noninverted trl-state
bus
tranceivers.
The
htgh
lmpedance
output
state
ls not
used.
The direction
of
U55
is
switched by BRW+
and
data ls transferred to the
processor
when
BRI+|
1s low and
from the
processor
to
J2
and
the rest of the
system when
low. The
directlon
of
U43
ls
controlled by
RW-.
Data
transfer
is
from the
processor
when
1ow.
The
system clock,
8
Mhz-,
and
control
bus signals
SRES+,
RW-,
LDS+,
UDS+,
and A9+ are
buffered by
tJ44,
Thts Schottky
trl-state
buffer
74521+0
is used
as a
bus driver
without
the tri-state mode.
SAGB
BUS
The Sage
interface bus ls comprised
of connectors
Jl
and
J2.
J1
lncludes the
address llnes
lnverted and buffered,
FC2- the
user/supervisor
bit,
and
PRTY-
which
ls
the
RAM
parity
exceptlon
interrupt line,
The
odd numbered
pins
of
Jl
are
all
connected
to
ground
for
signal
lsolation.
J2
includes buffered
and unbuffered slgnals.
The
buffered
lines lnclude
the data
lines, system
clock
8
I'lhz-,
system
reset
SRES+,
readfwrite RW-, lower data strobe LDS+,
upper data strobe
UDgl-,
and
address
strobe AS+.
The unbuffered
lines
are the two external
lnterrupt
inputs
12-
and
13-,
and data
transfer
acknowledge
DTACK-.
The
odd
numbered
plns
I
through
33
of
J2
are connected
to
ground.
Pins
35,
37r 39,
4t, 43,
and
45
are
connected
to
+5 volts. Pin 47
ls +12 volts
and
pln
49
is
-LZ
volts.
55