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SAGE
II SERVICE
KIT
CPU BOARD
CIRCUIT
DESCRIPTIONS
PAGE 4
OF SCHEMATIC
DIAGRAMS
XVII.O4
PAGE
4 OF
SCHE}TATIC
DIAGRAI.{S
:
This
section
contains
the
RAI',I,
parity
circuit.
RAI.{
ADDRESS
LOCATION
the
RAl"t
bus transcelvers,
and
the RAM
The arrangement
of the
RAI'{
schematlc is
mapped
to
match
the
actual
parts
placement
on the
prlnted
clrcuit
board,
and thus lt
can
be used
Eo
determine
the
physlcal
locatlon
of
a
particular
blt
or
address
group.
Refer
to the
parts
locatlon
drawlng for
the
followlng
dlscussion.
The
row
of
IC's across
the
top
of the
page
have
RAS0 connected
to
pln
4
and
are
deslgnated
as
R0I^I0
on the
board,
The second row
down
ls
ROWI
and
the thtrd
row
ls
R0W2 and
the
bottom
row ls
R0W3. The
ROW
designatlons
are sometlmes
referred
to as
BANKS
of memory,
ie.
BANKO,
BANKI, etc.
The 1ef
t slde
of
the
schematic has
the
low
byt,e RAt{ IC's
and the
rlght
slde
has
the
upper
byte.
The
lowest
order bits and
the
lowest
order
nlbbles
are
toward
the
left.
The two
coltrmns of
parity
IC's are
down
the
rniddle.
the
bit columns
are
numbered
across
the top
of
the
parts
locatlon
drawlng.
ADDRESS
LOCATIONS BY ROW
IN HEX
to
1FFFF
to
3FFFF
to
5FFFF
to
TFFFF
The
multiplexed
address
llnes
RAO-
to
RA7-
are
bussed
to
every
lntegrated
clrcult
in
the
array.
Ihe
four
coh:mn
address
strobe
slgnals
CASO- through
CAS3-
are bussed
to nibble
wlde
groups
of
columns
and
the
second
and
third
nlbbles
lnclude
the
parity
coltrmns.
Ttre lower
byte
wrl-te
enable llnes
LWO
and
LWI
are
bussed
similarly
to the
CAS as are
the upper
byte
write
enable llnes
IfW0
and
UI^II.
Ttre four
8T28 bus drlvers
U63,
tJ62,
U30,
and
V23
interface
the
RAl'l data
bus
to
the system
data
bus.
Antl-ringlng
reslstors
are
used ln
the
lnput
lines.
The
RWR-
signal ls not
used ln thls
conflguratlon
so that
the
RAM
data bus is
always
enabled
toward the
RAM.
RRD- enables
the bus
for
a read
cycle.
Row
0
from
00000
Row
1
from
20000
Row
2
from
40000
Row
3
from
60000
RAM
CONTROL
SIGNALS
64