Sage II - Terminal Problems

SAGE II
SERVICE KIT
CPU
BOARD CIRCUIT
DESCRIPTIONS
PAGE 4 OF
SCHEMATIC DIAGRAMS
(cont)
PARtrTY CIRCUIT
Two
9-bit
odd/even
parity generators/checkers
74L5280
U64
and
U3l
are
enpl-oyed
"
BRW+ enables the
output
of the
parity
RAMs
at the
NAND
gates
U50
and
U32
durlng a read cycle so
that
the
contents
can
be comblned
wjth
the data bus
for parlty
check.
Tf
the
parlty
is even
then
pln
-5
of
U64
and
U32
will both be
high and
no
parlty
interrupt will
occur. If
elther
PFL-
or
PFII-
go
low indlcating odd
pari.ty
the
lnterrupt
clrcui
t
on
page
3
wtl-l
l.atch,
During
a
'srlte
cyc
le the
0D
outputs
U64-6
data is odd and a
0
i,f even. The T
lnputs
bit
stored is the lnverse of
that
necessary
lt ls added lnto
the
parity
check
,
however
back
so
chat
parity
will
be even
when
read
errors
"
and
U31-6
store
a
I
if the
are low during a wrlte. The
to
produce
even
parlty
when
,
the
74LS00
gates
invert it
back
if there are no
memory
XVII"OS PAGB
5
OF SCHEHATIC DIAGRAUS
:
FTOPPY
DISK
CONTROTLER
The
floppy
disk controller sectlon uses
an
NEC 765 controller chip
to
take
care of all the
low
1evel interface
to the
floppy
disk. The
chip
ls used ln the interrupt
driven mode
with the
processor
respondlng
to an
asy'nchronous i-nterrupt from
the
765
for
every
byte
transferred.
An
FDC9216
digital
data separator
chlp
ls
used
for the
data separator.
There
are
two clisk
drlve
selects
provlded
f rom an
I/O
port.
Single/Doub1e denslty
select
1s
provlded
form
another
TlO
port
blt.
Wrlte
precomp
is
enabled/dtsabled
from another
T
IO
port
blt.
The
amount
of
wrlte
precomp
ls
determlned by
the
765
as
normal,
earlyr
or late
in
Lncrements
if
I25
nsec.
PSO, & PSI
from
the
765
determine the
select of
multi.plexer
U29,
which taps
off the
appropriate delay
from
the
serlal
in
parallel
out
shift
reglster
U20
to determine the
amount
of wrlte
precclmp.
The signal
FDIE+ is a
software controlled bit
from an
UO
port
which
ls
irseti
f-o
enabi-e otr disable
the
lnterrupts
generated
from
the
765.
The
RDY+
;1ne
whlch would normally
come
from
an
B"
disk drlve has been
connecued
t<i
another
I/0
port
bit
so that the ready
conditlon may be
ccntrol.
led
under sof,tware.
The
Til+
li,rre
which woul-d normal-ly
come
from
a
DMA controller to
signlfy
the
end
of a
DI'IA transf
er
now
also
is
generated
f
rom a
bit f rom an
T/O
p.rr:rf
sCI Lhe
transfers
may
be terminated
under direct sof tware
commands.
65