Sage II - Bus Error Due to Addressing Nonexistent Memory Locations

SAGE II SER\IICE
KIT
CPU
BOARD CIRCUIT
DESCRIPTIONS
PAGE
6
oF SCHEMATIC DIAGRAMS
(cont)
N,{ODEFT
OR.
SERIAL
PRINTER
PORT
Jq
is {:he
secand
serial.
porr
and is
al.so
iurplemented
using an
8251A U58.
firree
gates
of 1160
are
used
a.e
output for
positive
and negative
slgnal
leroels
a$
in Lhe
RS232
port
"
U59 and
U61
are
MC1488
packages.
U53
a
741,338 NAND ls
used
to
negative
logic
0R
inputs
CD- and RG-, the
output
of
which
cl-ocks
the
Ring
1
carrier
lnterrupt flipflop
U38.
The si.gna3"s
on the
system
side of the
port
are the same as
those
for
the
other
serial
port
wlth a few
exceptions.
The baud rate
clock
is
BRz+
f
rorn
U7
5
pin
L7
.
TX2I+
is connected
to
V73-2i. and
RX2I to
U73-19 on
page
2
whlch
Ls
Lhe interrupt
controller.
Also
connected to
U73
is
the
R1ng
/
carrier lnterrupt
slgnal MI+.
The reset
signal
RMI-
is from
U39
of thls
page.
The c.hip
select
pin
1l
is
f
rom
ul9-14
on
page
2.
PARAI,I,EL
PRINTER.
PORT
In
the
center
of
page
6
is IJ39
whj-ch
is
used
as
a
printer
port
and to
interface
some
hardware
control slgnals to
the software.
U39
1s
an
8255A-5
programmable
perlpheral
interface integrated
circuit.
U38
is
the
other
half
of
74L574
f1-ip
flop
used as an interrupt
latch
at the
MODEM
port
and serves
a
similar
function here.
CNI+
goes
to the
intelli-gent
interrupt
controller
U73-23 on
page
2. Other
connectlons
tcr
page
2
are
Lhe
buffered
address
lines at
pins
8
and
9,
the
chip select
CN-
from
Lrlg-ll,
and
the buffered
data lines
(
f/O data bus
)
from
U56.
SRES+,
RF
and WR-
are all
from
page
1.
The
T/0
control
slgnals
at
U39
lncl-ude
the
PRES-
to
U37-9,
SC+ Eo
U8-1 rhis
page,
SI+
page
I U65-5, and
RMI-
to
U38-13 this
page.
FDI+ froru
U21-18
page
5,
WP+ from
U4-10
on
page,
and
CD- from
U59-Ll also
of thls
page.
IEEE 488
following.
The
outpuLs are
to
tJ7
3'25
page
2, LEDR+ to
The lnput
signals lnclude
page
5,
RG- from
U61-8
this
This
j.s
&
standard porl
of ten referred
to as
the
HPIB,
GPIB, or
IEEE
488"
Implementation
here
comprises
U6,
7r
8,
and
one
gate
of U3.
U6
is
a TMS99!4
GPIB
adapter.
For
more
lnformation
on this
devlce refer
to
the
TMS99t4
GPIB
Adapter
Data Manual from
Texas
Instruments
Inc.
semi.conductor group,
Connections
to
page
I
include
HPI-
to
U36-1,
WR-
fraru
U&5*3u
SR-HS-
frorn
IJ44-9, and
RD-,
Connections from page
2
are
the
Il O
dat"a bus,
buf
f
ered
address
l-lnes
BAI
BA3,
chlp select
Hp-
f
rom
L?lq*t2 ancl
4 Flhz*
clock from
U69-13.
The
cleta llnes
are buffered
through
U7,
a
75160A octal
general
purpose
l-nterf;ace
bus
transceJ"ver.
The
control 1lnes are
routed
through
U8,
a
75X6?A
whlch
is
alsn
a
GPIB transceiver.
SC+ U8-1
is from
U39-15 of
this
page-
both
U7
and
U8
are
bi-directional
and further
lnformatlon
on
them tnay
be
found
j.n
the
Ltne
Driver and
Ltne
Receiver
Data
Book
from
67