Samsung CLP-610ND - System Diagrams; Block and Connection Diagrams

System Diagram
Samsung Electronics
Service Manual
6-1
6
6
6. System Diagram
6.1 Block Diagram
6.1.1 24ppm Main Controller Block Diagram(CLP-660)
DATA(0:15)
DATA(0:15)
ADDR(1:8)
CLP-660 MAIN Controller BlockDiagram
CPU
RM7065C
(64bit,533Mhz)
3.3V 1.3V
DDR1 Module
128MB(32MBx4)
DDR1 Module
(Extend)
256MB(64MBx4)
or
512MB(64MBx8)
64bit
DC-DC
5V to 2.5V,
1.25V
(DDR1)
2.5V, 1.25V
Panel
LCD module
5V
sysA D(63:0)
DQ(63:0)
DA(13:0)
DQ(63:0)
DA(13:0)
DQ(63:0)
DA(13:0)
UART
Engine
Controller
LPEC3
3.3V 1.8V
I/O
Engine
24V
5V
3.3V
to Syste m
DC-DC
5V to 3.3V
for System
3.3V
USB_device
ISP1582
3.3V(0.15A) 2.5V(0.15A)
ADDR(1:23)
System + Video
Controller
SPGPXm
(64bit,532MHz)
@SYS_CLK=118.44Mhz
DDR_CLK(3:0)LVDS
E-PHY
BCM5241
3.3V
MII
Modular
Jack
with LED,
COMBO
2.2.5 V
/1 .25V
NORFlash
MX29LV128MT
Flash
(16MB,NOR)
3.3V
EEPROM M24C64
3.3V
SCL/SDA
ADDR(1:23)
DATA(0:7)
ADDR(1:11)
RESET
XC61FN3112
3.3V
nF_RESET
nRESET
DC-DC(Core)
5V to
1.2V
1.2V
1.1.2V
DC-DC(Core)
5V to
1.3V
1.3V
1.3 V
DATA(0:15)
sysCMD(8:0)
nRST_LPEC3