Sanyo DC-C70 - LC78622 NE Digital Signal Processor

IC BLOCK DIAGRAM& DESCRIPTION
ICI02 LC78622NE (Digital Signal Processor)
No. I Pin Name I l/OI Function
1
I
DEFI
I
I IInputterminal for detectsignalof defed
.
21
TAI
I
I I Input terminal for test.
31
PDO I O IThe phase comparison output terminal for
E
4
Vvss
5
ISET
1
61
VVDD
k
7 FR
8
Vss
9
EFMO
Ilol EFMIN
—
I
I
I
external VCO control.
Ground terminal for built-in VCO
Resistance mnnection terminal for
electric cument adjustment of PDO output.
Built-in VCO power supply terminal.
VCQ frequency range adjustment.
Ground for Digital
EFM signal output terminal for slice level control.
EFM signal input terminal for slice level control.
11 TEST2
I
TEST pin. Normal time is non mnnection.
12 CLV+ o Output terminal for IXsc motor control.
13 CLV- 0 Output
terminal for Discmotor control.
14 VIP
o Change of rough setvo I phase control
Rough servo: “H”, Phase control: “L”
15 HFL
I Input terminal of track search signal.
16 I TES
I
I I Input terminal of tracking error signal.
17 I TOFF I O IOutput terminal of tracking off.
18 I TGL I O IOutput terminal for change of tracking ga
in.
19 I JP+
I O IOutput terminal for tracking jump fxmtrol.
I
al JP-
0 Output terminal for tracking jump control.
2t PCK o Clock monitor output terminal for EFM date
playback. (4.321 8 MHz)
22 FSEQ o Output terminal for detect of SYNC signal.
B DVDD
- +5V
24
CONT1 I/o
CONT2
CONT3
CONT4
CONT5
EMPH
Vo
I/o
I/o
I/o
T
This output can control at serial control from
micro processor.
Output terminal of de-emphasis mentor.
“H” . rk+emnhasis
331
C2F I O 10utput terminal of C2 flag
31 I
DOUT I O 10utput terminal of digital out
No.
Pin Name m
Function
S2
TEST3
I Test pin.
33
TEST4 I Test pin.
34
NC - Nonconnection.
35 MUTEL o Mute outputterminal for L-ch
36
LVDD
- Powersupply for L-ch
37
LCHO o Outputterminal for L-ch
28
LVSS - GND for L*h
33
RVSS - GND for R-ch
40
RCHO o Output terminal for R-ch
41 RVDD
- Power supply for R-ch
42 MUTER o Mute output terminal for R-ch
43
XVDD - Power supply of crystal oscillation
44
XOUT
o
Connection terminal of crystal oscillation (16.9344MHz)
45
XIN
I Connection terminal of crystal oscillation(16.9344MHz)
43
XVss - GND of crystal oscillation
47 SBSY
o Output terminal for synchronizing signal of
sub-cord block
48
EFLG o Output terminal for correction monitor of
Cl, C2,
Single and Double
49
Pw o Output terminal for sub-cord of P, Q, R, S, T, U and
W
B) SFSY
o Output
terminal for synchronizing signal of
sub-cord frame
51 I
SBCK
I
I I Input terminal for readout dock of sub-cord
521
FSX I O 10utput terminal of Synchronizing signal (7.35kHz)
-.
53 WRQ o Outp ut terminal for standby of sub-cord Q output
54
RWC I Input terminal of read I tie control
55 SQQUT
o Output terminal of sub-cord Q
55 COIN
I Input terminal of command from micro processor
57 CQCK
I
Clock input for reading sub-cord from SQQUT
58
RES I Reset (turn on: L)
93
TST11
o Teat pin
60
16M o 16.9344MHz
61
4.2M o 4.2336MHz
Q
TEST5 I Test pin
63
Cs
I Chip select terminal
64 TEST1
I Test pin
TST11TEST2 TEST4
EFMO
woo Wss
PDO ISET FR
PCK TAI TEST1 TESi3 TEST5
VW Vss
DEFI
EFMIN
FsEQ
CLV+
CLV-
WQ
Pw
SSCK
SSSY
SFSY
Cs
WRQ
SWUT
m
COIN
Rwc
ccwr2 CCMT4 Xvss
Xour
RVSS MUTER
LVSS
C2F
Ooln
(Nc)
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