Schweitzer Engineering Laboratories SEL-300G - Unlatch Trip; Generator Tripping; Generator Main Circuit Breaker Trip, TR1

4-14 SELOGIC
®
Control Equations
Date Code 20000616 SEL-300G Instruction Manual
Unlatch Trip
Once Relay Word bit TRIP is asserted to logical 1, it remains asserted at logical 1 until all
the
following conditions come true:
• Minimum Trip Duration Timer stops timing (logic output of the TDURD timer goes to
logical 0)
• Output of TR1 gate deasserts to logical 0
• One of the following occurs:
− SEL
OGIC Control Equation setting ULTR1 asserts to logical 1, or
− the front-panel TARGET RESET button is pressed, or
− the TAR R (Target Reset) command is executed via the serial port.
The front-panel TARGET RESET button or the TAR R (Target Reset) serial port command
primarily is used during testing. Use these to force the TRIP1 Relay Word bit to logical 0 if test
conditions are such that setting ULTR1 does not assert to logical 1 to deassert the TRIP1 Relay
Word bit automatically.
TRIP2 through TRIP4 operate similarly to TRIP1, as shown in Figure 4.6. The Relay Word bit
TRIP is the OR condition of the four primary TRIP1 bits.
GENERATOR TRIPPING
Generator Main Circuit Breaker Trip, TR1
It is necessary to trip the Generator Main Circuit Breaker to isolate the generator from the system
in response to many situations. The SEL-300G Relay elements and logic used to detect each of
the conditions are summarized in the table below.