Sharp CD-K1861V - Page 50

CD-K1861V
– 50 –
IC2 VHiLC78631E-1: Servo/Signal Control (LC78631E) (2/2)
Figure 50 BLOCK DIAGRAM OF IC
Pin
No.
FunctionTerminal Name Input/Output
51 XVSS — Crystal osccillator garound. Normaly 0v.
52 XOUT Output 16.9344 MHz crystal oscillator connections. Use a 33.8688 MHz Crystal oscillator for quadspeed playback.
53 XIN Input 16.9344 MHz crystal oscillator connections. Use a 33.8688 MHz Crystal oscillator for quadspeed playback.
54 XVDD — Crystal oscillator power supply.
55 RVSS — Right channel ground. Normaly 0V.
56 RCHN Output Right channel N output.
57 RCHP Output Right channel P output.
58* RVDD — Right channel power supply.
59* MUTER Output Right channel mute output.
60* SBSY Output Subcode block synchronization signal output.
61* EFLG Output C1 and C2 error correction state monitor.
62* PW Output Subcode P,Q,R,S,T,U and W output.
63* SFSY Output Subcode frame synchronization signal output. Falls when the subcode output goes to the standby state.
64 SBCK Input Subcode readout clock input. This is a Schmitt input.
65* DOUT Output Digital output.
66* FSX Output Outputs a 7.35 kHz synchronization signal generated by dividing the crystal oscillator frequency.
67 WRQ Output Subcode Q outputstandby output.
68 RWC Input Read/write control input.
69 SQOUT Output Subcode Q output.
70 COIN Input Input for commands from the control microprocessor.
71 CQCK Input Command input acousition clock. Also used as the SQOUT subcode readout clock input.
This is a Schmitt input.
72 RES Input Chip reset input. This pin must be set low temporary when power is first applled.
73* TESEF Output
74* CONT2 Output Output port.
75 16M Output 16.9344 MHz output. 33.8688 MHz output in 4x playback mode.
76 4.2M Output 4.2336 MHz output.
77 TEST5 Input Test input. A pull-down resistor built in.
78 CS Input Chip select input. A pull-down resistor is built in.
79 DEFI Input Defect detection signal input.
80 VCOC Input Variable pitch VCO control input.
One-bit D/A
converter pins
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note: The same potential must be to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
Unused input ports of general-purpose input/output ports (I/O) must be connected to 0V or set output port.
V/P
CLV+,CLV-
FSEO
PCK
EFMO
EFMI
DEFI
PDO1,PDO2
FR,ISET
FAST
VPDO
VCOC
XOUT
XIN
HFL,TES
JP+,JP-
SLD+,SLD-
TOFF,TGL, THLD
DOUT
EMPH
LRCKO,DFLRO, DACKO
MUTEL
LCHP,LCHN
RCHP,RCHN
MUTER
SBSY,SFSY, PW,SQOUT, WRQ
LRSY,ROMXA,
CK2,C2F
FSX,EFLG
SBCK
CS,RWC,
CLV
FRAME
SYNCHRONOUB
PROTECTION
PLL
FAST
DETECT
VARIABLE
PITCHRO
PKK
TJ
COMMAND
I/F
ADDRESS
GENERATOR
DRAM
EFM
DEMODULATION
SUB CODE
DEMODULATION
CIRC
(ECC)
DOUT
DATA
COMPENSATION
MUTE
ANTI-SHOCK I/F
D-ATT
DE EMPHASIS
DF
PQRT
DAC
15
13
14
22
21
9
11
79
2,
3
5,
7
1
80
52
53
19,20 28,29 30,31
23,24,
25
78,68
64 60,62,
63,67,69
65
32
34,35,
36
46
48,
49
56,
57
59
42,
43,
44,
45
66,
61