Sharp LC-30HV4U - Page 42

42
LC-30HV4U
LC-30HV4D
Pin No. Pin Name Type Description
1,33,48,75 DGND –– Digital GND (same as I/O)
39,62,100 DVDD –– Digital 2.5V Power
4-12,28-30, TEST01- TEST pin (Open or GND)
32,40-43, TEST26
78-85,99
13 EXTALTF O Extension 4fsc Alternate flag Output
14-23 EXTDYCO0- I/O Extension digital In/output
EXTDYCO9
24-25 DGNDRAM –– DRAM GND
26-27 DVDDRAM –– DRAM 2.5V Power
31 DVDDIO –– I/O 3.3V power
34-35 AGND –– OSC circuit GND
36 XI I Reference CLOCK Input
37 XO O Reference CLOCK
38 AVDD –– OSC circuit 2.5V power
44 RPLL I Test in/output (Connect GND)
45 SLA0 I I2C Bus Slave Address input select
46 SCL I I2C Bus Clock Input
47 SDA I/O I2C Bus data In/output
49 AGND –– fscDAC GND
50 AVDD –– fscDAC 2.5V Power
51 FSCO O fsc generator fsc output
52-53 AGND –– 8fsc PLL GND
54 FSCI I 8fsc PLL fsc Input
55 AVDD –– 8fsc PLL 2.5V Power
56 CKMD I CLK8 TEST mode select
57 CLK8 I/O CKMD=0.8fsc CLOCK output
CKMD=1.8fsc CLOCK input
58 RSTB I System Reset Input (Active Low)
59 ST0 O Internal signal monitor output
60 ST1 O Internal signal monitor output
61 NSTD O Abnormal detection monitor OUTPUT (L:Normal, H:Abnormal)
63-72 DYCO0-DYCO9 I/O Digital In/output
73 ALTF O 4fsc Alternate Auto Flag Output
74 LINE I Forced Line Input Select
(L:Normal, H:Forced)
76 KIL I External killer Input
(L:Standard, H:Forced)
77 CSI I Composite Sync (Active Low)
2 TESTIC1 I IC Selection TEST (GND)
3 TESTIC2 I IC Selection TEST (GND)
86 AVDD –– Y-DAC, C-DAC 2.5V power
87 CBPC O C-DAC Output
88 ACO O C-DAC Analog C Signal Output
89 AYO O Y-DAC Analog Y Signal Output
90 CBPY O Y-DAC, Output
91 AGND –– Y-DAC, C-DAC GND
92 AGND –– ADC GND
93 AYI I ADC Analog Composite Signal Input
94 VCLY O ADC Clamp Power output
95 VRBY O ADC Bottom Reference Voltage Output
96 VRTY O ADC Top Reference Voltage output
97 VCOMY O ADC Sync Reference Voltage
98 AVDD –– ADC 2.5V power
ËVHIPD6408+-1S (ASSY:IC7001)
3D Y/C separation LSI incorporates 4M-bit memory
» Pin mapping