Sharp LC-32GD8EE - Page 92

92
LC-26GA5E
LC-32GA5E
LC-32/37GD8E/RU
LC-32/37BT8E/RU
2.6.2. Pin Description (Continued)
7368868E STMicroelectronics Confidential 33/709
STi5516 Pin list
Confidential
Table 12: Programmable I/O pins
Pin Location I/O Function
Pad
type
PIO0[0:7]
A b
I/O Parallel input/output pin or alternative function P4
PIO1[0:7]
a
c
I/O P4
PIO2[0:7]
a
d
I/O P4
PIO3[0:7]
a
e
I/O P4
PIO4[0:7]
a
f
I/O P4
PIO5[0:7]
a
g
I/O P4
a. 5 V tolerant
b. U2, U1, U3, V4, V3, V2, V1 and W4
c. W3, W2, W1, Y3, Y2, Y1, AA4 and AE1
d. AF1, AD2, AE2, AF2, AF3, AD3, AE3 and AD4
e. AE5, AE4, AF5, AF4, AD6, AD15, AD5 and AE15
f. AF15, AD16, AE16, AF16, AC17, AD17, AF18 and AE17
g. AF17, AD18, AE18, AC19, AD19, AE19, AF19 and AD20
Table 13: Digital audio pins
a
Pin Location I/O Function
Pad
type
SCLK
B
AD13 O Serial clock C4
PCMDATA[1]
b
AE14 O PCM data out C4
PCMCLK
b
AE13 I/O External PCM clock input or internal PCM clock
output
C4
LRCLK
b
AF13 O Left/right clock C4
SPDIF
b
AC15 O Digital audio output C4
a. Note: Digital audio input pins PCMI_SCLK, PCMI_DATA and PCMI_LRCLK are alternate
functions for NOT_CD_REQ[1], I1284HOSTLOGICHIGH, and NOT_CD_REQ[0], on PIO port
3 bits [6:4]
b. 5 V tolerant