26
bus is used to convey row, column, and bank address information in a RAS/CAS
multiplexing style. For example, 1Gb(x8) device receive 14/10/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V
VDDQ.
The 1Gb DDR2 device is available in 60ball FBGA(x8) and 84ball FBGA(x16).
27
9. 32M x 16 bit DDRII Synchronous DRAM (U28-U29)
EtronTech EM68B16CWPA
a) Key Features
• JEDEC Standard Compliant
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Power supplies: VDD & VDDQ = +1.8V ± 0.1V
• Operating temperatue: 0 – 85 °C
• Supports JEDEC clock jitter specification
• Fully synchronous operation
• Fast clock rate: 333/400MHz
• Differential Clock, CK & CK#
• Bidirectional single/differential data strobe
-DQS & DQS#
• 4 internal banks for concurrent operation
• 4-bit prefetch architecture
• Internal pipeline architecture
• Precharge & active power down
• Programmable Mode & Extended Mode registers
• Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5
• WRITE latency = READ latency - 1 tCK
• Burst lengths: 4 or 8
• Burst type: Sequential / Interleave
• DLL enable/disable
• Off-Chip Driver (OCD)
-Impedance Adjustment
-Adjustable data-output drive strength
• On-die termination (ODT)
• RoHS compliant
• Auto Refresh and Self Refresh
• 8192 refresh cycles / 64ms
• Package: 84-ball 10x12.5x1.2mm (max) FBGA
- Pb and Halogen Free
To Next Page
