4. THE CPU
ANDLSI
PERIPHERAL LOGICS
4·'
General
[)
8284
Reedy cOntrol logic
aWA'T
READY
RESET
CLK
-----,
, ,
:8087-2
I I
"NT
...
,
CPU
SIH>2
Fig. 10
The
peripheral chips directly connected
to
the
CPU
(8086)
include: - the 8284
for
clock, reset and ready control; the
8259 for interrupt
control; the 8288
for
bus
control,
address
latches,
and
data
bus
buffers.
The
following describes
these
peripheral logics along
with
the
CPU
(8086) itself.
4·2 8086·2 microprocessor (16-bit parallel)
Highlights
(1) 16-bit parallel processing capability.
(2)
Basic
instruction
set
consisting
of
90
instructions.
(3)
Directly
addressable
1 MB memory
space.
(4)
14
x
16
bit
register
set.
(5)
8 or 16-bit arithmetic operation (including multiplica-
tion
and
division)
with
or
without
sign.
(6) 8MHz
single-phase
clock.
(7)
Maskable
(lNTR)
or
non-maskable (NMI) external
interrupt input.
(8)
Dual
mode operation (minimum/maximum). (MZ5600
is
used
maximum)
(9)
N-channel
MOS.
(10) Single +5V power supply.
(11) 40 pins DIP package.
-14-
Pin configuration
(top
view)
GND
.
Vcc(+5V)
~
ADl"
.
ADl5
AD
18
A16/S8
ADl2
AI7/S"
AD
11
A18/S5
AD
10
A19/S6
AD9
'BiIE/S7
AD8
IINIJiX
AD7
m
AD6
8086-2
HOLD(RQ/GR)
AD5
HLDA(RQ/GTI
)
AD"
lrIf('IOO()
AD8
1I/iO(Sf)
AD2
DT/1f(ST
)
ADI
IiEN(Sli)
ADO
ALE(QSO)
NIl I
INTA(QSl)
INTR
TEST
eLK
READY
GND
RESET
Fig.
11
,
Terminal
names
given in
parentheses
are
used
for
the
maximum mode. The
MZ-5600
uses
the 8086 in the maxi-
mum mode.
8086 functional outline
The 8086
has
maximum
and
minimum modes,
so
that
different pin configurations may
be
selected depending
on
~
the·
scale
of
the system
used.
The 8086
is
internally divided
into
an
execution
unit
(EU)
and
bus
interface
unit
(BIU).
The BIU controls a six-byte instruction queue
and
generates
address
information, while the
EU
interprets
and
executes
instructions.
Each
unit
operates asynchronously,
and
a
large
amount
of
processing
is
achieved with the pipeline
proces!,
sing
scheme.
The 8086
can
directly
access
up
to
1 MB
of
memory
space.
Also
it
can
handle data byte-by-byte (8 bits)
or
word-by-word (16 bits) depending on the status at the
AO
and
BHE terminals,
to
achieve
efficient
use
of
memory.
~
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