Sharp MZ-5500 User Manual

8·' Block diagram
8. MFD INTERFACE CIRCUIT
8237 DMAC
765 FDC
-
MZ-5600
t
~ _______ ....,,) Control signal
HLDA~
HRQ+-
L--- AO
DACKII----...::.~ DACK WR ~r8CompenS8tio~
r---~ DATA~~'~
ORQ
DREQI ~ delay lE- DRQ
WCLK.I'1'Ir------1
Wrlta
clock
I
WR DATA
\--- I
A7
RD
DATAIE-----I
~ RD DATA
IDO-7(~ _____________________ ~
8·2 Operational description
For read or write to the FDD, data are transferred under
the
high speed mode using the 8237DMAC.
The
following become necessary for the FDC to write or
read the FDD.
(1) The CPU furnishes the FDC and DMAC with command
and parameter and
the DMA channel 1 is opened.
• (2) When the FDC finds the corresponding sector on the
FDD, a DMA request (DRa) is issued to the DMAC.
(3) When the DMAC receives DRa, the DMAC issues a
HRa to the CPU.
(4) As the bus line is opened and HLDA signal is returned
when
the CPU receives H Ra, the DMAC sends back
OACK signal to the FOC.
(5) Data transfer takes place between the FOC and the
FOO under,the bus control by the OMAC.
a 8·3 Timings
Memory to FDC
SI
52
5'
SW
SI
CLK
ADR __ +-_-{
MRDC-------.,
RA5--- __ ---=!-.,r
..-.--~~====:...-
ISfima
VFO
~
L::Y
FDC to memory
CLK81
SELO
SELl
SEL2
SEL3
:~A OUT ------4---<
,'-- __ -'---1
... mu
RA/CA ------ _ _4___'
READY
LJ
8-4 Precompensation circuit
1. Block diagram
WR DATA
(FDC)
8MHz
C4
C6
CS
C7
CO
Cl
C2
CS
Y
C
B
A
~ DRAMDATA=
11' IOW--------...,
LSI51
READY-----~
L-------.J!
-35-
WR DATA
(FOD)
High DEN
PSI
PSO
(FDC)

Sharp MZ-5500 Specifications

General

Brand	Sharp
Model	MZ-5500
Category	Desktop
Language	English