Sharp MZ-5500 - Page 35

(2) PIe mask register clear
Since the IR-25 has been masked initially, it does not permit to accept
the interrupt unless the mask register is cleared.
PIe mask register 1/0 address: Master PIC ... 32H
Slave PIC .... 42R
The
IR-25 should be progranuned as foliows;
IN AL, 42H
AND AL, ODFR
OUT 42H, AL
(3) EOI generation
At the termination of the interrupt routine, there is a need of informing
the end of the interrupt processing to the PICo
HOV AL, 20R
OUT 40H, AL
OUT 30H, AL
IRET
\,
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