VDC1 (SP6102-035) pin functions
Table 38
Pin
No. Signal name
IN/OUT
1
RASO
-
-
OUT
6
RAS5
7
CKO
IN
8
CK1
IN
9
CK2
IN
10 OE
OUT
11
WE'
OUT
12 CAS
OUT
13
GND
IN
14 DISP
OUT
15
Vi5EO
-
-
OUT
17
\7Ei52
18 GDE
OUT
19
~
OUT
20
READY
OUT
21
RCS
OUT
22
RESET
IN
23
VA14
-
-
IN
26
VA17
27
:2~<::<::[1<:
OUT
28
HS
IN
29
BLANK
IN
30 RAS IN
31
DBIN
IN
32
DBD
OUT
33
CRL
OUT
34
CPUA
OUT
35
LOAD
OUT
36
Vcc
IN
37
DCK
OUT
38
S/L
OUT
39
CS
IN
40
VRAM
IN
41
Mwfc
IN
42
MRDC
IN
43
CA15
-
-
IN
45
CA17
46
DO
- -
IN
48
02
Description
Row
address select (RAS) signal
for
the
~M'
Durin"Ws~
access
timing,
the RAS
of
the
accessed
i
,
RAM
is
set
low.
During display timing, , 2, 4,
or
, 3, 5 are set low. During
RAM
rafresh,
RASO-5
are all set low.
Clock
input
for
400
rasters.
Clock
input
for
200 rasters.
External
clock
input
(from
SPCK).
I
VRAM
output
enabla. Since the
CPU
performs advancad writas
to
the
VRAM,
the
~
remains
at
low
I
VRAM
write
enable.
VRAM
column address select (CAS) signal. The CASH and
CASL
signals are created
from
this CAS
signal.
OV
input
Switches the CASH and
CASL
signals
for
CPU
eccess
and GDC
access.
Also used
as
a latch
timing
signal (CCAS)
for
the
8HE
and
AO.
:
;
V
RAM
data
bus
buffer
enable.
I
1
•
GDC data enable.
~
CPU
data enabla.
I
i
XACK
output
to
the CPU.
1
VRAM
row
and column address selact signal
(input
to
the S pin
of
MPX).
Reset
input
VRAM
address
input
from
the WDC
or
the GDC.
GDC
clock
output
i~
HSYNC
input
from
the
GDC
BLANK
input
from
GDC.
Row
address select (RAS)
input
from
the GDC.
Data
bus
in
(DBIN)
input
from
the GDC.
Direction select signal
for
bidirectional data bus
buffer.
High
for
VRAM
read;
low
for
VRAM
write
(Data
bus
direction).
CPU
read latch
clock
used
to
read
VRAM
data
into
the CPU.
Switches addrass buffers
for
CPU
access
and GDC
access
(for
diaplaying, refreshing or drawing). High
for
the CPU;
low
for
tha G DC.
Load signal
for
VDC2
LSI
+5V
power supply
Display
dot
clock
Shift/load
signal
for
the PIS conversion IC (LS166).
Chip select
input.
VRAM
chip select.
Memory
write
control
(~)
from
the CPU.
flemory
read
control
(MRDC)
from
the CPU.
Address
input
A
15-A
17
from
the CPU.
Data
input
from
CPU.
-62-
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