I
,
2)
INTR
CLK86
IR
input---.J
INTR
L
TJifI'A
L-..
__
----I'
Vector ( r
I ntarrupt vector
4-8
BUI
control logic
m Block dlllllram
808e
CPU
8288
so so
n
ST
n
n
iiROC
1iW'i'C
AIIWC
IORC
loic
AlotC
INTA
Fig. 22
Mlmary
IHd
control
output
Momory
wrIt.
_trol
output
Advtlncod mllllary wrIte control
output
1/0
IHd
control
output
I/O write control
output
Advoncod 1/0 write control
output
Interrupt
..
kn_odatt
(2) Description
When
the 8086
is
used in the maximum mode, com-
mands (RD,
WR,
INTA) are
output
as status informa-
tion
(SO-S2),
which are decoded by
the
8288
to
furnish
control signals
to
memory and I/O devices.
(3) Timing chart
eLK
During a
write
interrupt
Tl
T2
Ta
T4
I '
,
,
, '
.
____
r---t'_=!j.:J.'...,io-
MAX
85
1
,.....;.'----
~
l'lJJ'
,I
: I :
I I I I
-.:
:",MAX85
-oi
"'-MAX45
If
\ :
+-----"-.~-MA~X~
~~~'~-MAX--~-
. -:-
___
:,....J/',
:;
\L--""~~
During a
read
'T"'
,....
~'n:-
MAX80
--!
fMAX80
DT/R
••
I •
Fig.
23
4-9 Reset, ready circuit
1. Block diagram
~
Memory
0-
7FFFFH
AOOOOft-
BFFFFH
FCOOOH-
FFFFFH
-+-
________
_
I/O
O-IFFH
I/O
IOOft-UPH
-4-~--;-",
I/O
CTC
-I---+-+--r-'\
-
MZ-5600
8088-2
CPU
8284A
RESET
READY READY
RDY
CLK
CLK
2. Operational description
Yoeset
, For reset
of
the
8086 CPU,
the
alarm
Signal
.from the
power
supply and
the
rising edge
of
+5V
atthe
time
of
power
on
are detectad by
the
CR
time constant. The
reset
signal
to
the
CPU
is
Internally synchronized with
the
clock by
the
8284A.
Refer
to
the
section dlscuulng
the
power supply unit for
alarm timing.
2) Ready
Because the
MZ-5600 employs the non-ready system,
the
ready signal
is
returned
to
the
CPU
only when access
is
valid. Though
the
memory
or
I/O decoder signal
is
actually supplied
to
the 8284A, it makes
RDY
signal
delayed
in
synchronization with
CLK
in
the
WAIT
timing circuit for a device
that
needs wait.
The ready
signal
is
returned automatically from the
timeout circuit when
an
I/O
or
memory
in
the
XACK
area
is
tried
to
access,
to
send
NMI
to
the
CPU.
See below for wait
of
each device.
8M mode
5M mode
o
System RAM 0 IPL ROM
o Kanji/dictionary ROM
1
0
o 1/0 other than below
oSlO
0 RTC 0
PSG
0
PB
3 3
o CTC
olNTACK
0
INT
RET
15 15
o
VRAM
0110
(380H-3FFH)
XACK
XACK
o Memory other than
above
or
1
3. Timings chart
o 8MHz 1
WAIT
HITI
Tt
T2
T8
TW
o 611Hz
aWAIT
TI
T2
Ta
T4
TI(TI)
-23-
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