-
MZ-5600
CPU
commands and
addresses
are
latched
within
the
(5)
VDC2 (SP6102-034) - Video composition
VDC1. Display
addresses
DA
14 and
DA
15
are
latched
VDC2
functional outline
within
the WDC, and
are
not
latched
into
the VDC1.
a)
Background color
-
If
data
is
all
zeros, the VDC2
The decoder (DA14-17)
also
accepts refresh (RF) and
provides background
color
for
the window according
to
blank (BN) inputs. During refresh, the decoder activates
the
window
number.
all the chip selectors. During display,
it
activates
RASO,
b) Border color -
If
the logical
OR
of
the Blank
signal
2,4
or RAS1,
3,5
by using the DA14.
from the
GDC and the
BSC
(back screen)
signal
from
the
WDC
is
true, the VDC2 outputs a border color.
*
CDE
c)
Plane
priority
- The
priority
of
a plane
is
identified
by
ViWf-{>--
.-
comparing the data in VRAM1 and
VRAM2
with
the
CPUTiming
value
set
on the
I/O
port
by the comparator.
~-{>---
CDE
d)
Superimposition in the monochrome mode -
e)
Normal/reverse
video
display
for
each
window,
in
monochrome mode.
°READY
CR;~
-~'ID'
VDC2 (video composition) block diagram
IIRDC
IT
AB
A2
Al
02 01
DO
Vcc_
j
J J J
III
GND_
'lJ-
J
LOAD
-----;JJ
110
PORT
MW'i'C
r-
l
CR
I--
1
CLR
VRAII
wso
--.
I--
~
RCS
WSl~
> r---
~
BL~
:'i
I--
.
Fig.
81
VSLO----l
~
r---
~
1----'0'
VSL
1
----I
I--
~
r-
t---'
Q
NORMAL
1----'01
VSL2_
I--
REVERCE
NPXER
'--
":r
1----'0'
5L
'---
'----
DCK
,L
.--~
r-~
L.--
'--
510
~
BACK
511
~t-
OR
t---'
PRIORITI'
GROUND
r---
BORDER
COLOR
COLOR
512
Q
'--
~
~
~
'-----
Fig. 82
Table 39
VDC2 (SP6102-034) pin functions
Pin No. Signal name
IN/OUT
.
,
Description
,
,
1
WSO
IN
Window
select signal
from
WDC
2
WSl
3 VSLO
-
-
IN
VRAM
data select
inpl!t
from
the WDC.
5
VSL2
-~
6
LOAD
IN
Used
to
latch the HSYNC and
BLANK
signals
from
GDC, and the
VSLO-2,
WSO,
1, and
BSC
signals
from
the
WDC.
7
S/L
IN
Shift
load
input
(from
SP61
02-035).
8
DCK
IN
Dot
clock
input
(from
SP6012-035).
9
SOO
-
-
OUT
Serial data
output
to
palet resistor
11
S02
12
GND
IN
OV
input
13
SiO
- -
IN
Display data
from
the PIS converter (74166)
input
(serial).
15
Si2
"
/
16
BLNK
IN
Blank signal
input.
17
CS
IN
Chip select
input.
18
Al
-
-
IN
Address
bus
from
the CPU.
20
A3
,
21
DO
- -
IN
Data bus
from
the CPU.
23
02
24
Vcc
IN
5V
-64-
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