ri)nternal VDC2 configuration
.
sr.,·
Display
data
output
from the shift register has a delay of
one
display cycle plus four
dot
clocks with respect
to
O.()~
the
GDC
cycle. Therefore, other signals are also delayed
lit.
0
1
'.
by
using
the following logic:
rS,Ol
£,(\/50
D
D D
WSOD
WStD
UI
~,r.
It
FIF
8-
BLD
C,
Y'BU
]:
(.~SL,I
fj,
'.
\iSLI
i.:
t;
[l,:,
LO.jD
SIL
aY
SIlO
DCK
D
510
FIF
501
SI
I
SI2
D
FIF
f===~-~~=:[)
CK
~------------~~-4---C
Fig. 83
Input data
is
combined (AND) with VSlO-2 and
Bl,
and
is
timed by a
tYI=
,-0
flipflop. The
WSO,
WS1,
and
Bl
are
delayed further by two clock timings
to
provide back-
ground and border colors.
*
Plane
priority logic
Priority
mode
11/0
pon)
3
-bit
comparator
A2
~"O
{
Al
pori.
AO
A)B
B2
SIlO
~Ol
BI
SOli
BO
• • Back,mund
0010<
1/0
3
bit
ports
4-[
WSOD
SO
SI
WSlD
510----------'
511-------'
5[2-------------'
Fig. 84
C
CK
3bit
0
2-[
F!F
seJecto
Fig. 85
510
Sll
512
520
522
523
Background color data furnished
to
the I/O port
is
output when
the
display data
is
all
zeros. Data from the
I/O
port
is
switched for each window using
WSO-2.
* Monochrome mode' reverse video logic
I/O
1
4-to-1
port
selector
so
'ifS
OD
WSID
BLD
510
511
512
Fig.
86
-
MZ-5600
C
In
the monochrome mode, three pieces
of
display data
are combined
(OR). Reyerse video
is
accomplished on
the
data on
the
I/O port selected by
WSO
and 1. To
prevent
the
border area from being reversed, the display
data
is
combined (AND) with the Blank signal.
•
Output
logic
S20
3-bit.
SOO
S21
2-to-1
'selector
.
SOl
S22
.
S02
M
-
S
I/O
port
Fig. 87
(6) Register File (RFL)
74LS670
The palette feature
is
provided by the 74LS670. The
74lS670
is
a 4 x 4 bit high-speed static
RAM.
Two chips
are used
to
provide 8 x 4 bits
RAM
space, of which 8 x 3
bits are used for the palette feature.
The read
output
is
always enabled, and the address input
accepts
the
address information furnished by VDC2. The
col or actually displayed
is
determined by the data written
from the
CPU
into the
74lS670.
I
5
[0
VAAMdata
SI
1
5[2
54
A8,A'f'A6'A5'M
A8'A7'A6'A
ss
A4
GW
From
CPU
A2
WB
Al
WA
D10 D3
Q3
10
D8 Q3
D9
D2
Q2
D9
D2 Q2
D8
DI
QI
D8
DI
QI
LS670
LS670
08-10
--
.....
----+-'1-+-'
B
If
G
Fig. 88
-65-
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