Sharp MZ-5500 - Address Setup

Signal name
In/Out FUllction
IR-22-IR-26
.\
In °lnterrupt request input from the device on the 1/0
slot.
IR-22
For HD interface
lR-23
For , SFD interface
IR-24
Not used
IR-25
Not used
IR-26
For user's use
DACK2
Out
°System RAM refresh signal.
DREQO, DREQ3 In DDMA transfer request and ackllowledge signal.
°Channel 0 for the hard disk and the channel 3 for the
standard floppy disko
I
I
I
DACKO, DACK3
Out
CLK86, CL4M
OSC
Out
°CLK86 isthe CPU clock which is 4.9152HHz with the
MZ-5500 and 8MHz when the system switch-S is set off
and 4.9152MHz when the switch-5 is set on with the
MZ-S600. It is a narrow high per~od clock of 1/3 duty.
°CLK4M is 4MH and OSC is 14.7456MHz clock.
RESET Out
°Power-:-on-reset signal which is normally low. '
RSTSW Out ~The signal is forced low while the front panel RESET
switch is kept depressed. At the moment the switcll
is pushed, an NMI is issued to the CPU.
*See the next page for the timing chart.
5-3. 1/0 address setup
When an 1/0 port is to be expanded on the expansion slot by the user, the
port address must be set as in the table below in reference to the
specification such as accessing time of the device to be used.
Access time from IORC (tACC)
Port address
I
tACC< 300ns 180B - lBFH
300ns< tACC..c::. 550ns 300H - 3JFH
550ns< " tACCS 100;Us 3COH - 3FFH
*Because the access time shown in the table is just for reference, it will
need more st~dy before the actual designing.
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