Sharp MZ-5500 - Page 87

ANALOG CH C
DAO
TE ST
n
DAI
Vec 5V
iII
DA!
ANALOG CH B
m
LOCK
DA'
ANALOG CH A
U DA.
GND
I
!:I
DA5
IO A7
7
ZI
DA 11
IOA8
a
n
DA7
ICA6
ZIO
IOA4
10
18
'CA.
II
11
' O AI
U
11
IOAI JI
11
IOAO
14
16
fig.14 - 2 AY-3-8912 pin configuration
fable 14-1 AY-3-8912 signal description
Pin
No.
1
2
Signal name
ANALOG
CH C
TESTl
In/Out
Out
Function
Analog output channe1 C
Test pin during chip manufacture which
should be unconnected.
3
4
5
6
7 -
14
VCC
ANALOG
CH
B
ANALOG
CH
A
GND
IOA7 - 0
Out
Out
In/Out
+5V supply
Analog output
channel
B
Analog output
channe1
A
OV
1/0 port
15
16
1 7
] 8
19
20
CLOCK
RESET
A8
BDIR
BC2
BCI
\
In
In
In
In
In
In
Tone noise,envelope generator timing
reference input
(2MHz)
Input of a 10w
(0)
signal to this line at
the start,
it resets all registers.
Auxi1iary address bit which is provided to
permit a memory space expansion in
addition to the area specified by DA7 - DAO.
Bus direction
.Bus
control
1
Bus
control
2
These bus control signals control all
external and
internal bus
operation of
the
PSG. Signals
are decoded
in
the following
manner by the PSG.
BDIR
BC2 Bel
PSG
function
0
0 0
INACTIVE
The PSG/CPU bus
becomes
inactive and
DA7-DAO high
impedance.