Sharp MZ-5500 - Software Timer

4. Software timer
j) Hardware
One chip of the Z-80A CTC is used for the software timer of the MZ-5500 and
it has four channels. For the MZ-S600, two chips of the Z- 80A CTC which
have e ight channels are used.
Each channel has the specification as shown in Table 4-1. Channels, 4 to
7, however, are the specification applicable for the MZ-5600 only.
Fig.4-1 shows the block diagram of the MZ-5600 software timer. The CTC
controlling channels, 4 to 7, muat be omitted from the figure for the
MZ-5500. A timing control circuit is added to control the Z-80A CTC 1/0
read, write, interrupt acknowledge,
and interrupt return cycles by the 8086
CPU. Input of "OEDH" ancl "04DH" to
the 1/0 port (260H) for the interrupt
acknowledge cycle and thc illterrupt
return cycle correspond to "RETI" of
the Z-80 CPU.
A different CTC timing control
lASTS .....
circuit is provided for the
MZ-5500 D. .nd the MZ-5600, and
it has 3 waits for the 1/0
accessing timing of the MZ-5500
and 15 waits for the HZ-5600.
"' CHo-l .
IORQ
11Wtr
CiC ~ lt:./TOt
RSmC(I!)
eI oe"':.
nArr
(on1rc' vr
nnT
ClK/TR("~---'
L-t--~"Tmftf
~-+-~m
'----+---+4l1'T
~ CH4-7
llroincl t--____._-+----1f---tI41rn" "
Fig.4-1 Block diagram
Table 4--1 Channel specification
Ch 1/0 adr Mode Prescale Int Time constant, etc.
Model
0
210H
Timer 1/16 x 2 Refresh
timer
5500/
I58/2ms
5600
1
21] H
i
i
x
1
2
4
8
9600b/s
4800b/s
2400b/s
1200b/s
RS232C
Ch A
Tx, " Rx
2
212H
I
i
x 16
32
64
87
600b/s
300b/s
150b/s
110b/s
RS232C
Ch B
Tx, Rx
J
4
5
21311
21411
215H
Counter
t
t
--------
--------
~
0
0
0
0.832ms-213ms
0.052ms-1J.313ms
0.832ms-213ms
System timer
Reserved
Reserved
5600
only
6
7
216H
217H
t
t
-----------
----...------
0
0
0.832ms-213ms
3.328ms-852ms
Reserved
Reserved
\'