Sharp MZ-5500 User Manual

Pin functions
Table 36
Pin No.
Signal name
1
2 x
CCLK
2 DBIN
3
HSYNC·REF
4
VSYNC/ EX.
SYNC
5
BLANK
6 RAS
7
DRQ
8
DACK
9
RD
10
WR
11
AO
12
-
DBO - DB7
19
/
20
GND
21
LPEN
22
-
ADO - AD15
37
38
AD16, AD17
39
40
Vcc
IN/OUT
IN
OUT
OUT
I/O
OUT
OUT
OUT
IN
IN
IN
IN
I/O
IN
IN
IN
OUT
IN
-
MZ-5600
Description
Accepts a single-phase clock. The clock frequency is determined from the relationship between the
number of display characters per row and the horizontal display time. (One clock puis for ever 16 dots
(tow charactors»)
Output only when accessing the video memory, to place video memory output on the data bus.
Horizontal sync. signal. When the dynamic RAM control mode is selected, this signal may also be used
as a refresh timing signal.
May be used in the following two ways depending on whether the GDC is a master or a slave:
(1) When the GDC is a master, outputs a vertical sync. signal.
(2) When the GDC is a slave, accepts an external sync. signal.
(in the MZ5600 system the GDC is always master)
Erase
signal output used for the following conditions:
(1) Horizontal and vertical flyback periods.
(2) Between
the execution of a display stop command (e.g. RESET or STOP) and that of a START
command.
(3)
During video memory access for read/write.
Control signal furnished from the GDC to video memory.
In dynamic RAM mode, this is a basic timing for the RAM.
When high, functions as an address latch timing signal.
DMA request output (not used).
Indicates DMA transfer busy. (Not used)
Accepts a
low level signal when the CPU wants to read data or status flag out of the GDC.
The CPU
turns this input to low when it wants to write a command or parameter into the GDC.
Normally the least significant bit of the CPU address bus is connected to this pin, to specify data
types.
AO RD
WR
Function
0 0 1
Read status
flag.
1 0
1 Read data.
0
1 0 Write parameter.
1 1
0 Write command.
Bidirectional data bus.
OV return line.
Accepts a high
level when the light pen senses an optical input. At this time, the CPU can read the
display address latched in the GDC by using the LPEN command.
Bidirectional address/data bus connected to the video memory. During memory refresh, refresh
address
is output on the low order 8 bits of this bus. I n the text mode the AD 13 - AD15 are sued as
a line count output.
Video memory address output.
+5V power supply.
-57-

Sharp MZ-5500 Specifications

General

Brand	Sharp
Model	MZ-5500
Category	Desktop
Language	English