10.
RTC
REAL TIME CLOCK
10-1
Block diagram
10-3 Timing·chart
RP5CO I
Tt
T2 Ta
TW
TW
TW
T4
CSR'i'C
cs
CLK.
05C
IN
AO
OUT
IAO-IA8
I
Aa
I DO-1D8
VDD
+5V
~~~~
_Aour~
~----~------------~
lORD
CS
.-----
CLK86
PlC
IlfO'A
our
------------~c::::::>\----
6. -
10-4 RP5C01 (real-time clock)
(1) Highlights
1) Able
to
be
connected
directly
to
the
CPU.
i
2) Available as
either
a
24
hours
or
12
hours, AM/PM
clock.
3)
Contains a leap year calendar.
4)
All
time
data
is
output
in BCD codes.
10-2 Operational description
5) Adjustable by
trimmer
capacitor
6)
Allows a
battery
back-up.
7) Built-in
26
x 4
bit
RAM.
The
RP5C01
is
used
for
the
real time clock
of
the
MZ-5600
and
is
connect
parallel
to
the
8-bit I/O bus. Each
of
the
second, minute, hour, day
of
week,
day,
month,
and
year
registrers are
allocated
to
thirteen
addresses
and
represented
in a
BCD
number.
As
there
is
an alarm register
apart
from
the
calendar
registers, it
is
possible
to
interrupt
the
CPU
when
the
time
set in
the
alarm register
just
meet
the
time
in
the
calendar
resiters. They incorporate
two
13
x 4
battery
backed
up
RAMs.
(2)
8)
A timing pulse
of
1
Hz
or
16Hz available
as
an alarm.
Pin configuration
In
order
to
set
voltage stable for
input
and
output
pins
during power off,
the
real
time
clock
is
resistor pulled
down,
except
for
*WR
signal which
is
pulled
up
to
prevent
error writing
of
data
at
the
time
of
power
on
and
off.
*RD and *WR are delayed
by
the
flipflop in
order
to
main-
tain
the
address
setup
time
for
command.
cs
CS
ADJ
AO
At
A2
A3
Rn
GND
-
-
-
'"'
~
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
......
Vcc
-
OSCONT
OSCIN
ALARM
D3
D2
....
D1
"'"'
DO
WR
(3) Block diagram
OSCIN
-t
15
osc
f----o
J->
OSCOUT
'+-
I
p-
AD)
cs
~
fR
CLOCK
HOLD
"'--'
AD)
HOLD
~
CONTROLLER
6
IHZ.I
HZ
(52
(58
(54
-(s5
(56
(57
158
fi1
a
T1
4
ll
tzl tal
:1:
4
1
~l
1
1LARJ
REG'.sTEl
T-RESET
,
I
,
I
RD.
WR.ID)E
01
t
t
T t
T I f
A-RESET 'T
-1'
.1
.1
.1
.1
I
I
CJPARA~
I
1
I
I-I'
I
r
RD.WR.
1 f
T
T
T
T T
MODE
00
1
1
1
1
1
I
1
I
..:
1
..
/-t
SECONDS
MITES
HOURS
..
DAYS
~IJi
~
I
Jji
•
I
~
Ji
~
~-~
~T
~T
1T
T
T T
T
T
J
SO
SI
52 58
54
55
56
51
58
4 3 4 8 4 2 a 4
2
(o.!..
~
SO
I--
ADDRESS
BUS
~'-
DECODER
CONTROL
I--
SF
I-----
SF
TT 1 1
AO
Al
A2
AB
1111
DO
DI
D2
DB
-46-
ALARM
ALARM
OUTPUT
RD.WR,MODEIO
1
1
1
I
1
MODEII
I
I
en
'"
IIONTHS
YEARS
....
..
'"
I
~I~
"'"
-'
~
y.
T T
T
59
SA
SB
SC
4
I 4
4
2
14
SO-SC
INTERNAL
f--
~
26X4BIT
BUS
BUFFER
f--
RAM
I----t
~
~
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