0
\
~
r
f
,
~
Cc
Table
43
Direction
Signal
name
CPU
to
keyboard
Keyboard
to
CPU
DC
Send
data
'READY'
signal
'ifC
Strobe
Request
to
Send (strobe
for key data)
DK
READY
and
ACK signals
Send
data
SRK
None
Request
to
Receive (CPU)
(2)
Key
data transfer procedure
1) From keyboard
to
CPU
~r------------~[]~--~-
M Execution
of
~
R'
--,
key
pro~
Wait L
LJr------------------
Fig. 113
To
disable both the keyboard and
the
CPU
interrupt,
set both
DC
and
DK
to
zero.
Keyboard:
When
key search, code translation, and
other necessary entry data processing
is
completed, the keyboard starts transferring
entry data
to
the
CPU.
First, it waits until
DC
is
set
to
one. The waiting time
is
normally 3ms; for direct keys, it
is
1
ms.
If
a time·out occurred, the keyboard exits the
data send sequence.
When
DC
is
Set
to
one,
the keyboard sets
SRK
to
zero
to
interrupt
the
CPU.
CPU:
Keyboard:
CPU:
•
(
Keyboard:
CPU:
Keyboard:
CPU:
After acknowledging the interrupt, -the
CPU
verifies
that
DK
is
zero.
If
DK
is
one,
the
CPU
identifies the transferred data
as
noise, and exits
the
interrupt service
routine.
It theh sets STC
to
zero.
When
STC
is set
to
one, the keyboard
waits
until STC
is
set
to
zero. The maxi·
mum waiting time
is
5OOms.
If
a time-out
occurred, keyboard control returns
to
the
initialization routine.
When
verifying STe=
0,
the
keyboard send data
EB
and SRK
to
one.
Receiving the
EB,
the
CPU
sets STC
to
1
to
request
the
keyboard for the next data
send.
Seeing
STC
is
set
to
one, the keyboard
waits for
STC
to
be set
to
zero.
Sets
STC
to
zero
to
read' data from the
keyboard, then sets
STC again
to
one
to
request the keyboard for
the
next data
send.
When
STC
is
set to one,
the
keyboard sets
P.B.
and waits for STC
to
be reset
to
zero.
When
STC
is
set again
to
one,
it
sets
DK
to
zero.
Sets
STC
to
zero
to
read P.B. then sets STC
to
one
to
set the result
of
the parity check
into
DC.
If
a parity error occurred,
DC
is
zero;#-na
parity error occurred,
ne
is
1.
The
CPU
sets STC
to
one
to
complete
the
transfer sequence.
-77-
.-
MZ-5600
Keyboard:
When
STC
is
set
to
zero, the keyboard
reads the result of the parity check.
When
STC
is
set
to
one, it sets
DK
to
one
to
enable an interrupt from the
CPU,
and
completes the data transfer sequence.
If
a
parity error
was
detected, the keyboard
terminates the data transfer sequence, then
tries the same data send again.
* Repeat nine times.
2)
Form
CPU
to
keyboard
c.
A d4 I
d8
I
d2
c I
dl
I
dO
I
P.B
I
':~4''-.
_______
.......l.---1_._
SRK
.--------------------------~------------
CPU:
Keyboard:
CPU:
(
Keyboard:
CPU:
Keyboard:
CPU:
Fig.
114
Waits
for up
to
lOOms
for
DK
to
be set
to
one.
If
OKis still zero
lOOms
later, the
CPU
identifies it
as
a keyboard error and exits
the sequence. After verifying that
DK
is
one, the
CPU
sets
DC
and
STC
to
zero
to
interrupt the keyboard. '
When
the keyboard
is
interrupted by the
CPU,
it enters the data receive sequence
and verifies
DC=O.
If·
DC
is
one, the
key-
board identifies STe=O
as
noise, and exits
the interrupt sequence.
If
DC
is
zero, it sets
OK
to
zero.
Verifies
that
OK
is
zero
70IJs
after inter-
rupting the keyboard. The
CPU
then sets
STC
to
one
to
set d4, then resets
STC
to
zero again.
Seeing
STC
is
set to one, the keyboard
reads data when
STC
is
reset
to
zero.
Sets
STC
to
one
to
set data, then resets
STC
to
zero.
Reads
P.B.
to
check parity, then sets the
result of this parity check when
STC
is
set
to
1.
If
no parity error occurred, it sets
OK
to
one;
if
a parity error occurred,
DK
is
zero. The keyboard sets
OK
to zero when
STC
is
reset
to
zero.
Sets
STC
to
one
to
read the result of the
parity check.
It then temporarily sets SiC
to
zero and then sets it again to one,
to
terminate operations.
* Repeat
five
times.
(3) Keyboard check method
(A)
If the keyboard
is
locked up:
Checking the keyboard
p'rocessor
Connect the keyboard
to
the System Unit, then turn on the
system'
without .operating any keys.
If
only the
CAPS
indicator comes on,
ROM
check for the keyboard processor
(BOC49)
is
normal.
If
all
the indicators come on, it indicates
a
ROM
check error occurred. Probably the keyboard
processor
(80C49)
is
malfunctioning.
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