116
If
any bit
is
set
to
a one, then the corresponding data bus line will be used
as
an input. Conversely,
if
the
bit
is
reset,
the line will be used
as
an
output
.
During Mode 3 operation the strobe signal
is
ignored and the Ready line
is
held low. Data may be written
to
a
port
or read from a
port
by
the Z-80A-CPU at any time during Mode 3 operation. When reading a
port,
the data returned
to
the CPU will be composed
of
input data from
port
data bus lines assigned
as
inputs plus
port
output
register data from
those lines assigned
as
outputs.
4.4 SETTING THE
INTERRUPT
CONTROL WORD
The interrupt control word for each
port
has the following format:
used in Mode
3 only signifies interrupt control word
If
bit
D
7
= 1 the interrupt enable flip flop
of
the
port
is
set and the
port
may generate an interrupt.
If
bit
D
7
= 0 the
enable flag
is
reset and interrupts may
not
be generated.
If
an interrupt
is
pending when the enable flag
is
set, it will
then be enabled onto the
CPU interrupt request line. Bits D
6
,
D
5
,
and D
4
are used only with Mode 3 operation. How-
ever, setting bit D
4
of
the interrupt control word during any mode
of
operation will cause any pending interrupt to be
reset. These three bits are used
to
allow for interrupt operation in Mode 3 when any group
of
the
I/0
lines
go
to
certain
defined states. Bit D
6
(AND/OR) defines the logical operation
to
be performed in
port
monitoring.
If
bit D
6
= 1, an
AND function
is
specified and if D
6
=
0,
an
OR
function
is
specified.
For
example,
if
the AND function
is
specified, all
bits must
go
to
a specified state before an interrupt will be generated while the
OR
function will generate an interrupt
if any specified bit goes to the active state.
Bit D
5
defines the active polarity
of
the
port
data bus line to be monitored.
If
bit D
5
=
1,
the port data lines are
monitored for a high state while if D
5
= 0 they will be monitored for a low state.
If
bit D
4
= 1 the next control word sent
to
the PIO must define a mask
as
follows:
D7
Ds
MB
7
MB
5
MB
0
Only those
port
lines whose mask bit
is
zero will be monitored for generating an interrupt.
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