70
A.l
Technical
Data
of
Z 80A-CPU
1.0 ARCHITECTURE
A block diagram
of
the internal architecture
of
the Z-80A CPU
is
shown in Figure 1.0-1. The diagram shows all
of
the major elements in the CPU and it should be referred
to
throughout the following description.
13
CPU
AND
SYSTEM
CONTROL
SIGNALS
1.1
CPU
REGISTERS
INSTRUCTION
DECODE
&
CPU
CONTROL
rrr
+
5V
GND
¢
Z-SOA CPU
BLOCK
DIAGRAM
FIGURE
1.0-1
The Z-80A CPU contains 208 bits
of
R/W memory
that
are
accessible
to
the programmer. Figure 1.0-2 illustrates
how this memory
is
configured into eighteen 8-bit registers and four 16-bit registers. All Z-80A registers are imple-
mented using static RAM. The registers include two sets
of
six general purpose registers that may be used individually
as
8-bit registers or in pairs
as
16-bit registers. There are also two sets
of
accumulator and
flag
registers.
Special Purpose Registers
1.
Program ctmnter (PC). The program counter holds the
16
-bit address
of
the current instruction being fetched
from memory. The
PC
is
automatically increm
en
ted after its contents have been transferred
to
the address lines.
When
a program jump occurs the new value
is
automatically placed in the
PC
, overriding the incrementer.
2. Stack Pointer (SP). The stack pointer holds the 16-bit address
of
the current top
of
a stack located anywhere in
external system
RAM
memory. The external stack memory
is
organized
as
a last-in first-out (LIFO) file. Data can
be pushed onto the stack from specific
CPU registers or popped
off
of
the stack into specific CPU registers
through the execution
of
PUSH and POP instructions. The data popped from the stack
is
always the last data
pushed onto it. The stack allows simple implementation
of
multiple level interrupts, unlimited subroutine nesting
and simplification
of
many types
of
data manipulation.
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