83
NON
MASKABLE
INTERRUPT
RESPONSE
Figure 3.0-6 illustrates the request
/a
cknowledge cycle for the
non
maskable interrupt. This signal
is
sampled at the
same time
as
the interrupt line,
but
this line has priority over the normal interrupt and it can not
be
disabled under soft-
ware control. Its usual function
is
to provide immediate response to important signals such
as
an impending power
failure. The
CPU
response to a non maskable interrupt
is
similar
to
a normal memory read operation. The only differ-
ence being
that
the content
of
the data bus
is
ignored while the processor automatically stores the
PC
in
the external
stack and jumps to location
0066H . The service routine for the non maskable interrupt must begin
at
this location
if
this interrupt
is
used.
HALT
EXIT
Whenever a software halt instruction
is
executed the CPU begins executing NOP's until an interrupt
is
received
(either a non maskable or a maskable interrupt while the interrupt flip flop
is
enabled). The two interrupt lines are sam-
pled with the rising clock edge during each
T4
state
as
shown
in
Figure 3.0-7.
If
a non mask able interrupt has been
received or a maskable interrupt has been received and the interrupt enable flip-flop
is
set, then the halt state will be
exited on the next rising clock edge. The following cycle will then be an interrupt acknowledge cycle corresponding
to
the type
of
interrupt
that
was received .
If
both
are received at this time, then
th
e non maskable one will be acknowl-
edged since it has highest priority. The purpose
of
executing NOP instructions while in the halt state
is
to keep the
memory refresh signals active. Each cycle in the halt state
is
a normal M 1 (fetch) cycle except
that
the data received
from the memory
is
ignored and a NOP instruction
is
forced internally
to
the CPU. The halt acknowledge signal
is
active during this time
to
indicate
that
the processor
is
in the halt state.
NMI
A0
-
AI5
Ml
MREQ
RD
RFSH
INT
or
NMI
-
-
-
--
Last
M
Cycle
Ml
~
--~]_
Last
T Time
Tl T2
Ta
T,
~
~
~
~
~
u=.----
------
r------
-----
------
-----
------
------
------
-----
X X
\ I
\ I
\ J
\
NON
MASKABLE
INTERRUPT
REQUEST
OPERATION
FIGURE
3.0-6
--MI----~-------------------MI------------------~-----MI
HALT
INSTRUCTION
IS
RECEIVED
DURING
THIS
MEMORY
CYC
LE
HALT
EXIT
FIGURE
3.0-7
Tl
~
~
-----
-
-----
-
X
I
To Next Page
Loading...
