Siemens 7SR242 - Time Delayed Overcurrent Protection (51); Figure 3-6 Logic Diagram: Time Delayed Overcurrent Element

7SR242 Duobias Description Of Operation
©2010 Siemens Protection Devices Limited Chapter 1 Page 26 of 52
3.2.2 Time Delayed Overcurrent Protection (51)
Optionally two time delayed overcurrent elements are provided, each can be selected to either winding 1 or
winding 2.
51-n Setting sets the pick-up current level.
A number of shaped characteristics are provided. An inverse definite minimum time (IDMT) characteristic is
selected from IEC, ANSI or user defined curves using 51-n Char. A time multiplier is applied to the characteristic
curves using the 51-n Time Mult setting. Alternatively, a definite time lag delay (DTL) can be chosen using 51-n
Char. When Delay (DTL) is selected the time multiplier is not applied and the 51-n Delay (DTL) setting is used
instead. The full list of operating curves is given in Chapter 2 – ‘Settings, Configuration and Instruments Guide’.
Operating curve characteristics are illustrated in Chapter 3 – ‘Performance Specification’.
The 51-n Reset setting can apply a definite time delayed reset, or when configured as an ANSI characteristic an
ANSI (DECAYING) reset. If ANSI (DECAYING) reset is selected for an IEC characteristic, the reset will be
instantaneous. The reset mode is significant where the characteristic has reset before issuing a trip output – see
‘Applications Guide’.
A minimum operate time for the characteristic can be set using 51-n Min. Operate Time setting.
A fixed additional operate time can be added to the characteristic using 51-n Follower DTL setting.
Operation of the time delayed overcurrent elements can be inhibited from:
Inhibit 51-n A binary or virtual input.
51-n Inrush Action: Inhibit Operation of the inrush detector function.
1
General Pickup
51-n
51-n Setting
51-n Char
51-n Time Mult
51-n Delay (DTL)
51-n Reset
c
51-n Follower DTL
51-n Min. Operate Time
Wn-IL1
Wn-IL2
Wn-IL3
50/51
Measurement
&
L1 81HBL2
51-n Inrush
Action
Off
Inhibit
&
L2 81HBL2
L3 81HBL2
&
&
c
Pickup
trip
c
Pickup
trip
c
Pickup
trip
Inhibit 51-n
51-n Element
Enabled
Disabled
1
Figure 3-6 Logic Diagram: Time Delayed Overcurrent Element