LOGO! Manual
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Timing diagram for AND with RLO edge detection
1
Cycle
3
Q
2
123456789
10
4.2.3 NAND (AND Not)
The parallel connection of a number
of normally closed contacts is repre-
sented in a circuit diagram as follows:
Symbol in LOGO!:
The output of NAND only adopts the state 0 if all the inputs
have the state 1 (i.e. they are closed).
If an input pin of this block is not wired (x), then the follow-
ing applies to the input: x = 1.
Logic table for NAND
123Q
0 0 0 1
0011
0101
0111
1001
1011
1101
1110
LOGO! Functions
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