Sinclair ZX Spectrum Service Manual
Spectrum For Everyone https://spectrumforeveryone.com/
10
1.5 READ/WRITE OPERATIONS
The following description should be read in conjunction with the circuit diagrams.
1.5.1 Read Only Memory (IC5)
The CPU addresses the ROM directly during memory read cycles using the address bus A13-A0. MREQ and
RD enable the ROM and the ROM outputs respectively. A third input (CS) derived by the ULA (ROMCS)
selects the ROM, provided the higher order address bits A14 and A15 are both low. These are reserved
for accessing the RAM memory which starts with address 4000 (i.e. address A14 set). An external ROM IC
select input, supplied via the expansion port on pin 25A, selectively disables the on-board ROM by pulling
the select input high. By virtue of R33 placed on the ULA side of the ROM the ULA ROMCS output is
effectively inhibited. Interface 1 uses this mechanism allowing the CPU to read the extension ROM in the
interface for Microdrive and RS232 applications.
Links H and N, shown directly above IC5, allow a second source ROM to be fitted. The Hitachi (H) and NEC
(N) ROMs use different pins for the enable and select inputs (i.e. pins 20 and 27). The links allow the inputs
to be reversed accordingly.
1.5.2 Standard 16k RAM (IC6-IC13)
The eight 16k RAM ICs making up the standard 16k x 8 bit RAM memory are organised as a matrix of 128
rows x 128 columns. Thus, separate 7-bit row and column addresses are required to access any one of the
locations. These addresses are supplied by the CPU on address bus A13-A0 via an address multiplexer
IC3/IC4. The low order address bits A6-A0 give the row address and are selected at the beginning of the
memory access cycle when initially the RAS output from the ULA is high. Later, as the row address is
latched, RAS goes low selecting the high order address bits A13-A7 giving the column address.
The RAS/CAS outputs from the ULA are generated in sequence in response to MREQ and A14 from the
CPU. The DRAMWE output, also from the ULA is a decode of the RD/WR waveforms telling the RAM to
expect either a read or write cycle.
It is also apparent from the circuit diagram that the ULA can access RAM by generating a set of addresses
independent of those generated by the CPU. The address port for the RAM is therefore dualled by the
insertion of small value resistors (R17-R23) on the address multiplexer side of the RAM. This ensures that
where there is likely to be conflict between the ULA and CPU, the ULA address has priority. Priority is
assigned on the basis that the ULA must access the memory mapped display area in the RAM at set
intervals in order to build up the video for the TV display. If the ULA is about to access the RAM and it
detects either A14 or A15 (i.e. the CPU is also about to access the RAM) the ULA inhibits the CPU clock
temporarily halting the CPU memory transaction until its own transaction is completed.
Resistors R1 to R8, in series with the data bus lines, perform a similar function to the address port resistors
described above. They ensure that the ULA does not `see` CPU write data while the ULA is accessing the
RAM.
Refresh for the standard 16k dynamic RAM is accomplished during normal read cycles, ie most rows are
refreshed each time the ULA accesses the memory mapped displayed area during picture compilation;
the remaining rows are refreshed as a result of other read cycles also known to occur at regular intervals
within the refresh period.
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