Sinclair ZX Spectrum Service Manual
Spectrum For Everyone https://spectrumforeveryone.com/
8
1.2 ARCHITECTURE
The architecture of the Spectrum shown above is typical of many microcomputer systems in that it
comprises a single microprocessor board (in this instance a Z80A or u780 CPU), a read only memory (ROM),
an expandable RAM memory and an input/output section handling the keyboard, tape and TV display
functions. The latter is recognisable as the logic gate array (ULA) and the three functional blocks shown in
the right of the diagram.
The computer is built on a single printed circuit board which also includes a regulated power supply fed
from an external 9V power pack. The keyboard matrix is part of the upper case assembly and is connected
to the board via two ribbon cables KB1 and KB2. A description of each section follows.
1.3 Z80A CPU
The Z80A is an 8-bit single-IC central processing unit (CPU). It is clocked at 14.0 MHz from an external
source controlled by the logic gate array (ULA) and has a standard three bus input/output arrangement.
These buses are the Data Bus, Address Bus and Control Bus respectively.
1.3.1 Data Bus
D7-D10 constitutes an 8-bit bi-directional data bus with active high, tri-state input/outputs. It is used for
data exchanges with the memory and with the ULA.
1.3.2 Address Bus
A15-A0 constitutes a 16-bit address bus with active high, tri-state outputs. The address bus provides the
address for memory (up to 64k bytes) data exchanges and for data exchanges with the ULA. It is also used
during the interrupt routine when scanning the keyboard matrix.
1.3.3 Control Bus
The control bus is a collection of individual signals which generally organise the flow of data on the address
and data buses. The block diagram only shows five of these signals although others of minor importance
are made available at the expansion port.
Starting with memory request (MREQ), this signal is active low indicating when the address bus holds a
valid address for a memory read or memory write operation. Input/Output request (IORQ) is also active
low but indicates when the lower half of the address bus holds a valid I/O address for the ULA during I/O
read/write operations.
The read and write signals (RD and WR) are active low, and one or other is active indicating that the CPU
wants to read or write data to a memory location or I/O device. All the control signals discussed so far are
active low, tri-state outputs.
The last control signal described here is the maskable interrupt (INT). This input is active low and is
generated by the ULA once every 20ms. Each time it is received the CPU `calls` the `maskable interrupt`
routine during which the real-time is incremented and the keyboard is scanned.
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