Sony BDP-S485 - Page 72

3.3V LVTTL I/O,5V-tolerance, Motor Hall sensor input. The pin is spike-free at power-on
6 mA PDR,75K pull-up stage.
N1 FEFMO
A
.tuptuo CAD .lortnoc 1 rotom deeFtuptuO golan
N3 FEFMO2
A
.tuptuo CAD .lortnoc 2 rotom deeFtuptuO golan
Feed motor 3 control. DAC output.
A
lternative Function : Auxiliary servo input
Feed motor 4 control. DAC output.
A
lternative Function : Auxiliary servo input
Input of Focusing Signal (Negative)
A
lternative Function : Auxiliary servo input
Input of Focusing Signal (Positive)
A
lternative Function : Auxiliary servo input
L3 FOO
A
.rotasnepmoc ovres sucof fo tuptuo MDP .tuptuo ovres sucoFtuptuO golan
D1 FPDOCD
A
tupni evitagen laitnereffiD / CPA DC rof tupnI rotinoM rewoP resaLtupnI golan
E2 FPDODVD
A
tupni evitisop laitnereffiD / CPA DVD rof tupnI rotinoM rewoP resaLtupnI golan
T1 FEGAINSW1
A
1 .hctiws niag daeRtuptuO golan
P4 FEGAINSW2
A
.2 hctiws niag daeRtuptuO golan
P6 FEGAINSW3
A
.3 hctiws niag daeRtuptuO golan
3.3V LVTTL I/O,5V-tolerance, LDD serial interface data. The pin is spike-free at power-on
2,4,6,8 mA PDR,75K pulldown stage. The pin is not allowed to pull-up in circuit layout.
FE_MUTE1
3.3V LVTTL I/O,5V-tolerance, LDD serial interface CLK. The pin is spike-free at power-on
2,4,6,8 mA PDR,75K pulldown stage. The pin is not allowed to pull-up in circuit layout.
FE_MUTE2
3.3V LVTTL I/O,5V-tolerance, PC RS232 serial receive data. The pin is spike-free at poweron
2,4,6,8 mA PDR,75K pull-up stage
URXD
3.3V LVTTL I/O,5V-tolerance, PC RS232 serial transmit data. The pin is spike-free at poweron
2,4,6,8 mA PDR,75K pull-up stage.
UTXD
3.3V LVTTL I/O,5V-tolerance, High speed serial output port. (CLOCK) The pin is spike-free
2,4,6,8 mA PDR,75K pull-up at power-on stage.
3.3V LVTTL I/O,5V-tolerance, High speed serial output port (Data) The pin is spike-free at
2,4,6,8 mA PDR,75K pull-up power-on stage.
3.3V LVTTL I/O,5V-tolerance, General IO. The pin is spike-free at power-on stage.
2,4,6,8 mA PDR,75K pull-up
3.3V LVTTL I/O,5V-tolerance, LED Control Output. Initial 0 Output. The pin is spike-free at
2,4,6,8 mA PDR,75K pull-up power-on stage.
FE_EJECT
Read/Write gain switch 6
Read/Write gain switch 7
Read/Write gain switch 8. The pin is not allowed to pull-up in
circuit layout.
3.3V LVTTL I/O,5V-tolerance, General IO. The pin is spike-free at power-on stage. The pin is
2,4,6,8 mA PDR,75K pulldown not allowed to pull-up in circuit layout.
3.3V LVTTL I/O,5V-tolerance, General IO The pin is spike-free at power-on stage.
2,4,6,8 mA PDR,75K pull-up
3.3V LVTTL I/O,5V-tolerance, General IO. The pin is spike-free at power-on stage.
2,4,6,8 mA PDR,75K pulldown
Decoupling Pin for Reference Voltage of Main and Sub
Beams
G2 IN
A
A
nalo
g
In
p
ut
Input of Main Beam Signal (A)
G1 INB
A
nalo
g
In
p
ut
Input of Main Beam Signal (B)
olanA CNI2H
g
In
p
ut
Input of Main Beam Signal (C)
H1 IND
A
nalo
g
In
p
ut
Input of Main Beam Signal (D)
K3 INE
A
nalo
g
In
p
ut
Input of Sub-Beam Signal (E)
K4 INF
A
nalo
g
In
p
ut
Input of Sub-Beam Signal (F)
J4 ING
A
nalo
g
In
p
ut
Input of Sub-Beam Signal (G)
J3 INH
A
nalo
g
In
p
ut
Input of Sub-Beam Signal (H)
Sledge Inner Limit Input, Active Low. The pin is spike-free at
power-on stage.
Multiplexer Output 1 for Signal Monitoring. The pin is not
allowed to pull-up in circuit layout.
Multiplexer Output 2 for Signal Monitoring. The pin is not
allowed to pull-up in circuit layout.
U2 FEGIO6 Analog Output
Analog OutputFEGIO4 T3
Analog OutputFEGIO5U1
T2 FEGIO2
FEGIO3T6
U6 FEGIO12
T5 FEGIO13
FEGIO10U3
U5 FEGIO11
R4 FEGIO0
R6 FEGIO1
C1 FOIN Analog Input
Analog InputFOIPC2
P1 FEFMO3 Analog I/O
N5 FEFMO4 Analog I/O
W5 FEFG
Analog Output
W3 FEGIO7
T4 FEGIO8
3.3V LVTTL I/O,5V-tolerance,
6 Ma,75k pull-up
V3 FEGIO9
P2
FEMPXOUT2
K5 HAVC Analog Output
N6
FEMPXOUT1 Analog Output
V4 FELIMIT_
BDP-S485
6-6