Sony BDP-S485 - Page 71

A
D25 RDQ24
_
B I/O
Memory data bit 24
A
E25 RDQ25
_
B I/O
Memory data bit 25
A
H27 RDQ26
_
B I/O
Memory data bit 26
A
H28 RDQ27
_
B I/O
Memory data bit 27
A
C25 RDQ28
_
B I/O
Memory data bit 28
A
D24 RDQ29
_
B I/O
Memory data bit 29
A
C24 RDQ30
_
B I/O
Memory data bit 30
A
C23 RDQ31
_
B I/O
Memory data bit 31
P25 RDQM0
_
BO
Memory data mask bit 0
R24 RDQM1
_
BO
Memory data mask bit 1
A
D26 RDQM2
_
BO
Memory data mask bit 2
A
E26 RDQM3
_
BO
Memory data mask bit 3
R27 RDQS0
_
B I/O
Memory positive data strobe bit 0
R28 RDQS0
__
B I/O
Memory negative data strobe bit 0
P28 RDQS1
_
B I/O
Memory positive data strobe bit 1
P27 RDQS1
__
B I/O
Memory negative data strobe bit 1
A
G27 RDQS2
_
B I/O
Memory positive data strobe bit 2
A
G28 RDQS2
__
B I/O
Memory negative data strobe bit 2
A
F28 RDQS3
_
B I/O
Memory positive data strobe bit 3
A
F27 RDQS3
__
B I/O
Memory negative data strobe bit 3
A
D27 RODT
_
BO
Memory on die termination enable
A
D28 RRAS
__
BO
Memory row address strobe
A
A21 RVREF
_
3 I
Memory VREF
R23 RVREF
_
4 I
Memory VREF
A
E28 RWE
__
BO
Memory write enable
Y26 RRESET
_
BO
Memory reset
A
O/IKCT7D
JTAG ICE clock / JTAG boundary scan clock
A
O/I IDT8D
JTAG ICE data in / JTAG boundary scan data in
A
F6 TDO I/O
JTAG ICE data out / JTAG boundary scan data out
A
E7 TMS I/O
JTAG ICE mode select / JTAG boundary mode select
A
F7 TRST
_
I/O
JTAG ICE reset
A
B3
A
VDD12
_
USB
_
1P
_
1 Power
1.2V Analog power for USB
A
A3
A
VDD33
_
USB
_
1P
_
1 Power
3.3V Analog power for USB
A
B6
A
VSS12
_
USB
_
1P
_
1 Ground
A
nalog ground for USB
A
A5
A
VSS33
_
USB
_
1P
_
1 Ground
A
nalog ground for USB
A
A6
A
VSS33
_
USB
_
1P
_
1 Ground
A
nalog ground for USB
A
B1 USB
_
1P
_
DM
A
nalo
g
USB port3 differential serial data bus (minus)
A
B2 USB
_
1P
_
DP
A
nalo
g
USB port3 differential serial data bus (plus)
A
C3 USB
_
1P
_
VRT
A
nalo
g
USB reference resistor
A
C4
A
VDD12
_
USB
_
2P
_
1A Power
1.2V Analog power for USB
A
A4
A
VDD33
_
USB
_
2P
_
2 Power
3.3V Analog power for USB
A
B5
A
VSS12
_
USB
_
2P
_
1A Ground
A
nalog ground for USB
A
D1 USB
_
2P
_
DM0
A
nalo
g
USB port1 differential serial data bus (minus)
A
C1 USB
_
2P
_
DM1
A
nalo
g
USB port2 differential serial data bus (minus)
A
D2 USB_2P_DP0
A
nalog
USB port1 differential serial data bus (plus)
A
C2 USB
_
2P
_
DP1
A
nalo
g
USB port2 differential serial data bus (plus)
A
D3 USB
_
2P
_
VRT
A
nalo
g
USB reference resistor
A
C9 EFPWRQ Power
2.5V power for E-fuse programming
F5
A
VDD33
_
REC Power
HVGA analog power
D4
A
VDD33
_
LD Power
TX0 analog power
C5
A
VDD33
_
COM Power
PLL/BG 3.3V analog power
F6
A
VSS33
_
REC Ground
HVGA analog ground
C4
A
VSS33
_
LD Ground
TX0 analog ground
D5
A
VSS33
_
COM Ground
PLL/BG 3.3V analog ground
E5
A
VDD12
_
COM Power
PLL 1.2V analog power
E6
A
VDD12
_
REC Power
A
DC analog power
F7
A
VSS12
_
COM Ground
PLL 1.2V analog ground
G7
A
VSS12
_
REC Ground
A
DC analog ground
A
2 TXVP
_
0
A
nalo
g
Ethernet TD+
B4 TXVP
_
1
A
nalo
g
Ethernet RD+
B3 TXVN
_
0
A
nalo
g
Ethernet TD
A
4 TXVN
_
1
A
nalo
g
Ethernet RD
D6 REXT
A
nalo
g
External reference resistor
A
5 TANA
_
0
A
nalo
g
Ethernet analog test pin #0
B5 TANA
_
1
A
nalo
g
Ethernet analog test pin #1
J6
A
GND33
_
1A
A
nalo
g
Ground
A
nalog Ground
L7
A
GND33
_
2
A
nalo
g
Ground
A
nalog Ground
M
A
GND33
_
3A
A
nalo
g
Ground
A
nalog Ground
G6
A
GND12
_
1A
A
nalo
g
Ground
A
nalog Ground
M6
A
GND12
_
2A
A
nalo
g
Ground
A
nalog Ground
G4
A
UX1 Analo
g
I/O
A
uxiliary Input
E4
A
VDD12
_
1A
A
nalo
g
Power
(
1.2V
)
Power Pin
L5
A
VDD12
_
2A
A
nalo
g
Power
(
1.2V
)
Power Pin
J5
A
VDD33
_
1A
A
nalo
g
Power
(
3.3V
)
Power Pin
L6
A
VDD33
_
3A
A
nalo
g
Power
(
3.3V
)
Power Pin
3.3V LVTTL I/O,5V-tolerance, Frequency selection signal output, or LDD serial interface data
Slow slew,2, 4, 6, 8mA PDR, or I2C SDA. The pin is spike-free at power-on stage.
75K pull-up
3.3V LVTTL I/O,5V-tolerance,
High frequency modulation mode selection signal output, or
Slow slew,2, 4, 6, 8mA PDR,
LDD serial interface command enable. The pin is spike-free at
75K
p
ulldown
power-on stage.
N2 FEDMO
A
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3.3V LVTTL I/O,5V-tolerance, Eject/stop key input, active low. The pin is spike-free at poweron
6 mA PDR,75K pull-up stage.
L4 EQBIAS
A
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U4 FEEJECT_
P5 FECFREQ
FECMODR3
BDP-S485
6-5