Sony BKM-142HD - Page 58

7-4
BKM-120D/127W/129X/142HD
7-4
2
3
4
5
ABCDEFGH
1
BX (2/2) BKM-129XBX (2/2) BKM-129X
MB89613R-651 (IC501)
28
27
26
24
23
22
21
20
OSC
CLOCK CONTROL
RESET(WDT)
C-MOS I/O PORT
C-MOS I/O PORT
I/O PORT
C-MOS OUT PORT
EXT. BUS INTERFACE
RAM
ROM
TIME BASE TIMER
8 BIT
PMW TIMER
PULSE WIDTH
COUNT TIMER
16 BIT
TIMER COUNTER
8 BIT
SERIAL 1
8BIT
SERIAL 2
BUZZER OUT
I/O PORT
OPEN DRAIN
EXT. INTERRUPUT
OPEN DRAIN
OUT PORT
CPU
F MC-8L
2
X0
X1
RST
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
MOD0
MOD1
29
30
31
32
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
INTERNAL BUS
59
58
57
56
55
54
52
51
50
53
33
P20/BUFC
P37/PTO
P36/WTO
VCC
P35/PWC
P34/EC
P33/SI1
P32/SO1
P31/SCK1
P30
VSS
1
2
3
64
63
62
61
60
P47/S12
P46/SO2
P45/SCK2
P44/BZ
P43
P42
P41
P40
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
P50
P51
P52
P53
P54
P55
P56
P57
VCC
N.C.
VSS
P60/INT0
P61/INT1
P62/INT2
P63/INT3
P64
8 BIT
X25040S (IC503)
8
1
5
7
6
4
3
X DECODE
LOGIC
512 BYTE
ARRAY
STATUS
REGISTER
WRITE
PROJECT
LOGIC
COMMAND
DECODE
AND
CONTROL
LOGIC
Y DECODE
DATA REGISTER
WRITE
CONTROL
AND
TIMING
LOGIC
32
64
32
32X32
32X32
64X32
48
2
CS
SO
WP
VSS
VCC
HOLD
SCK
SI