Sony CFD-S45L - Block Diagram - CD Section

CFD-S45L/S47L
5-3. BLOCK DIAGRAM — CD SECTION —
– 19 – – 20 –
M
38 33 35
18
11
10
12
13
14
79
23
20
21
22
26
25
24
• Signal path
• R-ch : same as L-ch.
: CD
27
PD1
RF AMP
FE AMP
39
36
37
PD2
LD
PD
E
F
VC
42
41
51
17
18
19
13
LD ON
SWITCH
Q701
LASER
DIODE
CONTROL
SERIAL/
PARALLEL
CONVERTER
DECODER
RF O
FOK
C. OUT
SENS1
SENS2
IIL
TTL
DATA
XLT
CLK
XRST
TTL
IIL
TRACKING
PHASE
FOCUS
PHASE
COMAND
6 16 757456171521 8 9 62
65
67
TAO FEO
SLO
RF AMP & SYSTEM SERVO PROCESSOR
IC701
DIGITAL SIGNAL PROCESSOR
IC703
VREF
TRACKING
COIL
DRIVE
26
27
25
7
3
15
FOCUS
COIL
DRIVE
T+
F+
F-
T-
2
1
SLED
MOTOR
DRIVE
12
11
SPINDLE
MOTOR
DRIVE
SL+
SP+
SP-
OUT1
OUT2
SL-
TRACKING
COIL
FOCUS
COIL
A
C
B
D
E
F
LD
PD
OPTICAL PICK-UP
BLOCK
(KSS-213C)
TIN
FIN
MUTE
SLIN
SPI
INPUT1
INPUT2
OPTICAL PICK-UP
DRIVE
IC702
LOADING MOTOR DRIVE
IC703
M702
SLED
MOTOR
M
M701
SPINDLE
MOTOR
2
8
7
LOADING
MOTOR
DRIVE
3
5
14
4
6
7
M
M651
LOADING
MOTOR
(OPEN)
(CLOSE)
CLS-O
OPEN-O
OPEN-I
CLS-I
S651
XRST
10
SENS2
9
SENS1
12
SQSO
11
SQCK
1
SCOR
16
CLK
98
MUTE
15
XLAT
17
DATA
RF
FOK
CNIN
SEIN
DATO
XLTO
CLKO
XRST
MDP SPOA XLON SENS SQSO SQCK SCOR DATA XLAT CLOK SYSM
XTAI XTAO
SERVO
AUT
SEQ.
EFM DEMODULATOR
SERIAL
INTERFACE
D/A
INTERFACE
SUB CODE
PROCESSOR
CPU INTERFACE
DIGITAL
CLV
S701
(LIMIT)
SYSTEM CONTROL
IC501 (1/2)
70
•
71
X701
16.9344MHz
DIGITAL
FILTER
&
D/A
CONVERTER
AOUT1
LOUT1
76
74
AOUT2
LOUT2
CD L-CH
R-CH
1
MAIN
SECTION
PWM
AMP
PWM
AMP
CD
04