Sony HCD-DZ500F - Page 50

5050
HCD-DZ500F
HCD-DZ500F
•Waveforms
– DMB10 Board –
• IC Block Diagrams
IC602 MC14052BDR2 IC203 NJM2235V (TE2)
IC3601 PCM1803DBR
– I/O Board –
– DMB10 Board –
VINL 1
VINR
2
VERF1
3
VERF2
4
VCC
5
AGND
6
PDWN 7
BYPAS
8
FSYNC
9
LRCK
10
MODE120
MODE0
19
FMT1
18
FMT0
17
OSR16
SCKI15
VDD
14
DGCD
13
DOUT
12
BCK
11
Single-End
/Differential
Converter
5 th Order
Delta-Sigma
Modulator
5 th Order
Delta-Sigma
Modulator
Reference
Single-End
/Differential
Converter
× 1/64 (× 1/128)
Decimation
Filter
with
DC Cut Filter
Power Supply
Clock and Timing Control
Serial
Interface
Mode/
Format
Control
– MAIN Board –
200 ns
2.4 Vp-p
5.3 Vp-p
20.3 ns
7 IC108 rk (XFSOIN)
1 V/DIV, 10 ns/DIV
6 IC509 qg (Xin)
1 V/DIV, 100 ns/DIV
– I/O Board –
9 IC201 e; (VOUTa)
1 V/DIV, 20 µ s/DIV
0 IC201, IC202 wf (CYOUTa)
500 mV/DIV, 20 µ s/DIV
qa IC201, IC202 wa (CbOUTa)
500 mV/DIV, 20 µ s/DIV
1.7 Vp-p
H
H
1.7 Vp-p
H
qs IC201, IC202 qk (CrOUTa)
500 mV/DIV, 20 µ s/DIV
1.7 Vp-p
H
3 Vp-p
1
2
3
4
6
5
7
8
IN 1
SW 1
SW 2
VDD
VIN 3
OUT
GND
IN 2
BIAS
BUFFER
4 IC102 <xx. (XTALI)
1 V/DIV, 10 ns/DIV
5 IC102 <z., (YUV3)
500 mV/DIV, 20 µ s/DIV
3 IC102 ea (FED)
100 mV/DIV, 1 ms/DIV
2 IC102 es (TEO)
500 mV/DIV, 1 ms/DIV
1 IC102 6 (DVDRFIP)
200 mV/DIV, 100 ns/DIV
37 ns
1.8 Vp-p
H
700 mVp-p
0.3 Vp-p
0.5 Vp-p
1.5 Vp-p