Sony HCD-V808 - VIDEO Section IC Block Diagrams

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– 82 –
– VIDEO Section –
IC101 CXD8567AM
1INIT
2
3
4
5
6
7
8
9
10
11
12
13
14
D Vdd 2
SYSM L1 (+)
ATT A Vdd L
SHIFT L2 (+)
LATCH A Vss L
256FSO X Vss
TEST1 512IN
D Vss X OUT
MCKSEL X Vdd
XBCK A Vss R
DATA R2 (+)
LRCK A Vdd R
MUTE L R1 (+)
MUTE R D Vdd 1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MODES/P
ATT
IIR
FIR3FIR2FIR1
PLMPLM
MUTE
CIRCUIT
CLOCK
GENERATOR
AC
DITHER
DC
DITHER
3RD ORDER
NOISE SHAPER
SAMPLE
HOLD (X1)
TIMING CIRCUIT
IC201 CXD1852AQ
IC271 BU6257FV-E2
VSS
XTLOO
XTLO1
VDD
HA2 HA3
HD0 HD1 HD2 HD3 HD4 HD5 HD6
VDD
VSS
HD7
MA3 MA4 MA2 MA5 MA1
VSS
MA6 MA0
BC
TCKI
TDI
TENAI
TDO
VST
HA1
CLOCK
HA0
XRST
XHIRQ
XRW
XHDT
XHCS
DOIN
BCKI
DATI
LRCI
C2PO
VDD
XTL2I
XTL2O
VSS
VDD
FSXI
BCKO
LRCO
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DATO
99DOUT
98CLK0O
97XSGRST
96CSYNC
95CBLNK/FSC
94FID/FHREF
93VSYNC
92HSYNC
91VSS
31 VSS
32 MA7
33 MA8
34 XRAS
35 XMWE
36 XCAS2/MA9
37 XCAS0
38 MD7
39 MD8
40 MD6
41 MD9
42 MD5
43 MD10
44 VDD
45 VSS
46 MD4
47 MD11
48 MD3
49 MD12
50 MD2
51 MD13
52 MD1
53 MD14
54 MD0
55 MD15
56 XOSDEN
57 OSDB
58 OSDG
59 OSDR
60 VDD
123456789101112131415161718192021222324252627282930
VDD DCLK B/Cb7 B/Cb6 B/Cb5 B/Cb4 B/Cb3 B/Cb2 B/Cb1 B/Cb0 G/Y7 G/Y6 G/Y5 G/Y4 G/Y3 VSS VDD G/Y2 G/Y1 G/Y0 R/Cr7 R/Cr6 R/Cr5 R/Cr4 R/Cr3 R/Cr2 R/Cr1 R/Cr0 XVOE VSS
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VIDEO POSTPROCESSOR
&
SYNC GENERATOR
CLOCK
RESET
CLOCK
TEST
HOST
INTERFACE
CD-ROM
DECODER
D-RAM
INTERFACE
MPEG
SYSTEM
DECODER
MPEG
AUDIO
DECODER
MPEG
VIDEO
DECODER
EACH
CIRCUIT
BLOCK
CHARACTER
SIZE
REGISTER
HORIZONTAL
ADDRESS
REGISTER
WRITE
ADDRESS
COUNTER
HORIZONTAL
SIZE
COUNTER
HORIZONTAL
POSITION
COUNTER
HORIZONTAL
ADDRESS
COUNTER
VERTICAL
ADDRESS
REGISTER
VERTICAL
SIZE
COUNTER
VERTICAL
POSITION
COUNTER
VERTICAL
ADDRESS
COUNTER
1
2 3 6
4
5 7 8 9 10
1116 15 14 13 1217181920
OSCILLATOR
CIRCUIT
DATA INPUT
SHIFT REGISTER
PROTECT
CIRCUIT
DISPLAY CONTROLLER
DATA REGISTER
CHARACTER
GENERATOR ROM
12 × 18 BIT
× 255 WORD
CHARACTER DATA
8 BIT × 288 WORD
CHARACTER DATA
3 BIT × 288 WORD
COLOR DATA
3 BIT × 288 WORD
VIDEO RAM
DATA SELECTOR
OUTPUT CONTROL
BACKGROUND
CONTROLLER
DATA REGISTER
TEST CIRCUIT
HSYNC
VSYNC
VB
BLK1
VC1
RBLK GBLK
BBLK
VR VG
VSS
TEST OSCIN
OSCOUT
CKOUT VDD RESET CLK CSB DATA
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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