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DocID025833 Rev 4 47/55

UM1724 Hardware layout and configuration

9--109GND-10

11 - IOREF 12 11 PA5 PA12 12

13 PA13

(3)

RESET 14 13 PA6 PA11 14

15 PA14

(3)

+3V3 16 15 PA7 PB12 16

17 PA15 +5V 18 17 PB6 - 18

19 GND GND 20 19 PC7 GND 20

21 PB7 GND 22 21 PA9 PB2 22

23 PC13 VIN 24 23 PA8 PB1 24

25 PC14 - 26 25 PB10 PB15 26

27 PC15 PA0 28 27 PB4 PB14 28

29 PH0 PA1 30 29 PB5 PB13 30

31 PH1 PA4 32 31 PB3 AGND 32

33 VBAT PB0 34 33 PA10 PC4 34

35 PC2

PC1 or

PB9

(4)

36 35 PA2 - 36

37 PC3

PC0 or

PB8

(4)

38 37 PA3 - 38

1. Default state of BOOT0 is 0. It can be set to 1 when a jumper is on pin5-7 of CN7.Two unused

jumpers are available on CN11 and CN12 (bottom side of the board).

2. U5V is 5 V power from ST-LINK/V2-1 USB connector and it rises before +5V

3. PA13 and PA14 share with SWD signals connected to ST-LINK/V2-1, it is not recommend to

use them as IO pins if ST-LINK part is not cut.

4. Please refer to Table 9: Solder bridges for detail

Table 21. STMicroelectronics Morpho connector on NUCLEO-F401RE,

NUCLEO-F411RE (continued)

CN7 odd pins CN7 even pins CN10 odd pins CN10 even pins

Pin No. Name Name Pin No. Pin No. Name Name Pin No.

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