ST STM32F101xx series User Manual

PM0075
Doc ID 17863 Rev 1 5/31
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
● Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
● Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
● High-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 256 and 512 Kbytes.
● Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
● The Cortex-M3 core integrates two debug ports:
– JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
– SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols please refer to the Cortex M3 Technical
Reference Manual
● Word: data/instruction of 32-bit length
● Half word: data/instruction of 16-bit length
● Byte: data of 8-bit length
● FPEC (Flash memory program/erase controller): write operations to the main memory
and the information block are managed by an embedded Flash program/erase
controller (FPEC).
● IAP (in-application programming): IAP is the ability to re-program the Flash memory of
a microcontroller while the user program is running.
● ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the boot loader while the
device is mounted on the user application board.
● I-Code: this bus connects the Instruction bus of the Cortex-M3 core to the Flash
instruction interface. Prefetch is performed on this bus.
● D-Code: this bus connects the D-Code bus (literal load and debug access) of the
Cortex-M3 to the Flash Data Interface.
● Option bytes: product configuration bits stored in the Flash memory
● OBL: option byte loader.
● AHB: advanced high-performance bus.

ST STM32F101xx series Specifications

General

Series	STM32F101xx
Category	Microcontroller
Core	ARM Cortex-M3
Flash Memory	16 KB to 128 KB
GPIO Pins	Up to 80
Operating Voltage	2.0 V to 3.6 V
ADC	12-bit, up to 16 channels
Timers	Up to 3 timers
Communication Interfaces	I2C, SPI, USART

Summary

Introduction

Glossary

Overview

Features

Lists key features of the Flash memory, including density, organization, and interface capabilities.

Flash Module Organization

Details the memory organization based on device density, page size, and block structure.

Reading/Programming the Embedded Flash Memory

Introduction

Introduces the process of reading and programming the STM32F10xxx embedded Flash memory.

Read Operation

Explains how to read data from Flash memory, covering interfaces and prefetch buffer functionality.

Instruction Fetch

Details Cortex-M3 instruction fetching via I-Code and literal pool access via D-Code.

D-Code Interface

Describes the D-Code interface, an AHB interface for CPU access to Flash memory.

Flash Access Controller

Explains the arbiter that manages read requests from prefetch/I-code and D-Code interfaces.

Flash Program and Erase Controller (FPEC)

Introduces the FPEC block responsible for Flash programming and erase operations.

Key Values

Lists the essential key values (KEY1, KEY2) required to unlock the FPEC.

Unlocking the Flash Memory

Details the sequence to unlock the FPEC block and FLASH_CR register for write access.

Main Flash Memory Programming

Explains the procedure for programming the main Flash memory in 16-bit increments.

Standard Programming

Describes the standard half-word write operation for programming the main Flash memory.

Flash Memory Erase

Introduces methods for erasing Flash memory, including page and mass erase.

Page Erase

Outlines the step-by-step procedure for erasing a single page of Flash memory.

Mass Erase

Details the recommended sequence for a complete Flash memory mass erase operation.

Option Byte Programming

Explains how to program option bytes, including unlocking and writing procedures.

Option Byte Erase Procedure

Describes the sequence for erasing option bytes.

Protections

Covers mechanisms to protect Flash memory against unwanted access.

Read Protection

Details activation and management of read protection using option bytes.

Unprotection (Read Protection)

Explains the steps required to disable read protection on the Flash memory.

Write Protection

Describes the granularity and application of write protection for Flash memory pages.

Unprotection (Write Protection)

Details how to disable write protection under different scenarios.

Option Byte Block Write Protection

Explains the write protection mechanisms for the option bytes themselves.

Option Byte Description

Describes the purpose and configuration of the various option bytes.

Register Descriptions

Flash Access Control Register (FLASH_ACR)

Describes the FLASH_ACR register, controlling Flash access parameters like prefetch and latency.

FPEC Key Register (FLASH_KEYR)

Details the FLASH_KEYR register, used to provide keys for unlocking the FPEC.

Flash OPTKEY Register (FLASH_OPTKEYR)

Describes the FLASH_OPTKEYR register, used for unlocking option byte programming.

Flash Status Register (FLASH_SR)

Explains the FLASH_SR register for monitoring operation status and errors.

Flash Control Register (FLASH_CR)

Details the FLASH_CR register for initiating and controlling Flash operations.

Flash Address Register (FLASH_AR)

Describes the FLASH_AR register, used to specify addresses for Flash operations.

Option Byte Register (FLASH_OBR)

Explains the FLASH_OBR register for reading the programmed option bytes.

Write Protection Register (FLASH_WRPR)

Details the FLASH_WRPR register for read-only access to write protection settings.

Flash Register Map

Provides a map of Flash interface registers and their reset values.

Revision History