ST STM32F101xx series User Manual

Reading/programming the embedded Flash memory PM0075
20/31 Doc ID 17863 Rev 1
Table 7. Option byte organization
Address [31:24] [23:16] [15:8] [7:0]
0x1FFF F800 nUSER USER nRDP RDP
0x1FFF F804 nData1 Data1 nData0 Data0
0x1FFF F808 nWRP1 WRP1 nWRP0 WRP0
0x1FFF F80C nWRP3 WRP3 nWRP2 WRP2
Table 8. Description of the option bytes
Flash memory
address
Option bytes
0x1FFF F800
Bits [31:24] nUSER
Bits [23:16] USER: User option byte (stored in FLASH_OBR[9:2])
This byte is used to configure the following features:
– Select the watchdog event: Hardware or software.
– Reset event when entering Stop mode.
– Reset event when entering Standby mode.
Note: Only bits [16:18] are used, bits [23:19]: 0x1F are not used.
Bit 18: nRST_STDBY
0: Reset generated when entering Standby mode.
1: No reset generated.
Bit 17: nRST_STOP
0: Reset generated when entering Stop mode
1: No reset generated
Bit 16: WDG_SW
0: Hardware watchdog
1: Software watchdog
Bits [15:8]: nRDP
Bits [7:0]: RDP: Read protection option byte
The read protection helps the user protect the software code stored in Flash
memory. It is activated by setting the RDP option byte.
When this option byte is programmed to a correct value (RDPRT key = 0x00A5),
read access to the Flash memory is allowed.
(The result of RDP level enabled/disabled is stored in FLASH_OBR[1].)
0x1FFF F804
Datax: Two bytes for user data storage.
These addresses can be programmed using the option byte programming
procedure.
Bits [31:24]: nData1
Bits [23:16]: Data1 (stored in FLASH_OBR[25:18])
Bits [15:8]: nData0
Bits [7:0]: Data0 (stored in FLASH_OBR[17:10])
0x1FFF F808
WRPx: Flash memory write protection option bytes
Bits [31:24]: nWRP1
Bits [23:16]: WRP1 (stored in FLASH_WRPR[15:8])
Bits [15:8]: nWRP0
Bits [7:0]: WRP0 (stored in FLASH_WRPR[7:0])

ST STM32F101xx series Specifications

General

Series	STM32F101xx
Category	Microcontroller
Core	ARM Cortex-M3
Flash Memory	16 KB to 128 KB
GPIO Pins	Up to 80
Operating Voltage	2.0 V to 3.6 V
ADC	12-bit, up to 16 channels
Timers	Up to 3 timers
Communication Interfaces	I2C, SPI, USART

Summary

Introduction

Glossary

Overview

Features

Lists key features of the Flash memory, including density, organization, and interface capabilities.

Flash Module Organization

Details the memory organization based on device density, page size, and block structure.

Reading/Programming the Embedded Flash Memory

Introduction

Introduces the process of reading and programming the STM32F10xxx embedded Flash memory.

Read Operation

Explains how to read data from Flash memory, covering interfaces and prefetch buffer functionality.

Instruction Fetch

Details Cortex-M3 instruction fetching via I-Code and literal pool access via D-Code.

D-Code Interface

Describes the D-Code interface, an AHB interface for CPU access to Flash memory.

Flash Access Controller

Explains the arbiter that manages read requests from prefetch/I-code and D-Code interfaces.

Flash Program and Erase Controller (FPEC)

Introduces the FPEC block responsible for Flash programming and erase operations.

Key Values

Lists the essential key values (KEY1, KEY2) required to unlock the FPEC.

Unlocking the Flash Memory

Details the sequence to unlock the FPEC block and FLASH_CR register for write access.

Main Flash Memory Programming

Explains the procedure for programming the main Flash memory in 16-bit increments.

Standard Programming

Describes the standard half-word write operation for programming the main Flash memory.

Flash Memory Erase

Introduces methods for erasing Flash memory, including page and mass erase.

Page Erase

Outlines the step-by-step procedure for erasing a single page of Flash memory.

Mass Erase

Details the recommended sequence for a complete Flash memory mass erase operation.

Option Byte Programming

Explains how to program option bytes, including unlocking and writing procedures.

Option Byte Erase Procedure

Describes the sequence for erasing option bytes.

Protections

Covers mechanisms to protect Flash memory against unwanted access.

Read Protection

Details activation and management of read protection using option bytes.

Unprotection (Read Protection)

Explains the steps required to disable read protection on the Flash memory.

Write Protection

Describes the granularity and application of write protection for Flash memory pages.

Unprotection (Write Protection)

Details how to disable write protection under different scenarios.

Option Byte Block Write Protection

Explains the write protection mechanisms for the option bytes themselves.

Option Byte Description

Describes the purpose and configuration of the various option bytes.

Register Descriptions

Flash Access Control Register (FLASH_ACR)

Describes the FLASH_ACR register, controlling Flash access parameters like prefetch and latency.

FPEC Key Register (FLASH_KEYR)

Details the FLASH_KEYR register, used to provide keys for unlocking the FPEC.

Flash OPTKEY Register (FLASH_OPTKEYR)

Describes the FLASH_OPTKEYR register, used for unlocking option byte programming.

Flash Status Register (FLASH_SR)

Explains the FLASH_SR register for monitoring operation status and errors.

Flash Control Register (FLASH_CR)

Details the FLASH_CR register for initiating and controlling Flash operations.

Flash Address Register (FLASH_AR)

Describes the FLASH_AR register, used to specify addresses for Flash operations.

Option Byte Register (FLASH_OBR)

Explains the FLASH_OBR register for reading the programmed option bytes.

Write Protection Register (FLASH_WRPR)

Details the FLASH_WRPR register for read-only access to write protection settings.

Flash Register Map

Provides a map of Flash interface registers and their reset values.

Revision History