ST STM32F101xx series User Manual

Reading/programming the embedded Flash memory PM0075
14/31 Doc ID 17863 Rev 1
Standard programming
In this mode the CPU programs the main Flash memory by performing standard half-word
write operations. The PG bit in the FLASH_CR register must be set. FPEC preliminarily
reads the value at the addressed main Flash memory location and checks that it has been
erased. If not, the program operation is skipped and a warning is issued by the PGERR bit in
FLASH_SR register (the only exception to this is when 0x0000 is programmed. In this case,
the location is correctly programmed to 0x0000 and the PGERR bit is not set). If the
addressed main Flash memory location is write-protected by the FLASH_WRPR register,
the program operation is skipped and a warning is issued by the WRPRTERR bit in the
FLASH_SR register. The end of the program operation is indicated by the EOP bit in the
FLASH_SR register.
The main Flash memory programming sequence in standard mode is as follows:
● Check that no main Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
● Set the PG bit in the FLASH_CR register.
● Perform the data write (half-word) at the desired address.
● Wait for the BSY bit to be reset.
● Read the programmed value and verify.
Note: The registers are not accessible in write mode when the BSY bit of the FLASH_SR register
is set.
2.3.4 Flash memory erase
The Flash memory can be erased page by page or completely (Mass Erase).
Page Erase
A page of the Flash memory can be erased using the Page Erase feature of the FPEC. To
erase a page, the procedure below should be followed:
● Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_CR register
● Set the PER bit in the FLASH_CR register
● Program the FLASH_AR register to select a page to erase
● Set the STRT bit in the FLASH_CR register
● Wait for the BSY bit to be reset
● Read the erased page and verify

ST STM32F101xx series Specifications

General

Series	STM32F101xx
Category	Microcontroller
Core	ARM Cortex-M3
Flash Memory	16 KB to 128 KB
GPIO Pins	Up to 80
Operating Voltage	2.0 V to 3.6 V
ADC	12-bit, up to 16 channels
Timers	Up to 3 timers
Communication Interfaces	I2C, SPI, USART

Summary

Introduction

Glossary

Overview

Features

Lists key features of the Flash memory, including density, organization, and interface capabilities.

Flash Module Organization

Details the memory organization based on device density, page size, and block structure.

Reading/Programming the Embedded Flash Memory

Introduction

Introduces the process of reading and programming the STM32F10xxx embedded Flash memory.

Read Operation

Explains how to read data from Flash memory, covering interfaces and prefetch buffer functionality.

Instruction Fetch

Details Cortex-M3 instruction fetching via I-Code and literal pool access via D-Code.

D-Code Interface

Describes the D-Code interface, an AHB interface for CPU access to Flash memory.

Flash Access Controller

Explains the arbiter that manages read requests from prefetch/I-code and D-Code interfaces.

Flash Program and Erase Controller (FPEC)

Introduces the FPEC block responsible for Flash programming and erase operations.

Key Values

Lists the essential key values (KEY1, KEY2) required to unlock the FPEC.

Unlocking the Flash Memory

Details the sequence to unlock the FPEC block and FLASH_CR register for write access.

Main Flash Memory Programming

Explains the procedure for programming the main Flash memory in 16-bit increments.

Standard Programming

Describes the standard half-word write operation for programming the main Flash memory.

Flash Memory Erase

Introduces methods for erasing Flash memory, including page and mass erase.

Page Erase

Outlines the step-by-step procedure for erasing a single page of Flash memory.

Mass Erase

Details the recommended sequence for a complete Flash memory mass erase operation.

Option Byte Programming

Explains how to program option bytes, including unlocking and writing procedures.

Option Byte Erase Procedure

Describes the sequence for erasing option bytes.

Protections

Covers mechanisms to protect Flash memory against unwanted access.

Read Protection

Details activation and management of read protection using option bytes.

Unprotection (Read Protection)

Explains the steps required to disable read protection on the Flash memory.

Write Protection

Describes the granularity and application of write protection for Flash memory pages.

Unprotection (Write Protection)

Details how to disable write protection under different scenarios.

Option Byte Block Write Protection

Explains the write protection mechanisms for the option bytes themselves.

Option Byte Description

Describes the purpose and configuration of the various option bytes.

Register Descriptions

Flash Access Control Register (FLASH_ACR)

Describes the FLASH_ACR register, controlling Flash access parameters like prefetch and latency.

FPEC Key Register (FLASH_KEYR)

Details the FLASH_KEYR register, used to provide keys for unlocking the FPEC.

Flash OPTKEY Register (FLASH_OPTKEYR)

Describes the FLASH_OPTKEYR register, used for unlocking option byte programming.

Flash Status Register (FLASH_SR)

Explains the FLASH_SR register for monitoring operation status and errors.

Flash Control Register (FLASH_CR)

Details the FLASH_CR register for initiating and controlling Flash operations.

Flash Address Register (FLASH_AR)

Describes the FLASH_AR register, used to specify addresses for Flash operations.

Option Byte Register (FLASH_OBR)

Explains the FLASH_OBR register for reading the programmed option bytes.

Write Protection Register (FLASH_WRPR)

Details the FLASH_WRPR register for read-only access to write protection settings.

Flash Register Map

Provides a map of Flash interface registers and their reset values.

Revision History