ST STM32F103 series Application Note

Implementation example AN2739
10/26
When the MCLK clock is enabled (by configuring the relative configuration register), MCKI
jumper (JP18) should be configured in the 2<>3 position in order to drive the MCLK signal
from the STM32F103xx I
2
S interface to the codec MCLKI pin.
The default codec configuration used in this application note is:
● I
2
S standard: I
2
S Phillips (can be changed to MSB or LSB standards)
● MCLK clock enabled at 256 × F
S
frequency rate and PLL disabled. (Disabling the
MCLK clock might lead to a reduced audio quality due to the high accuracy needed on
the alternative clocks: WS or CK)
● The default output is the headphone but the configuration can be changed before or
during the application execution (using the up/down joystick push-buttons).
Codec configuration steps
● Power up the codec (supply voltage) and activate it (pull the PDN pin high). This
operation causes all the codec registers to reset.
● Select the audio protocol (Phillips, MSB or LSB) by writing to Mode Control 1 register at
address 0x04.
● Select the MCLK rate (256 × F
S
) if the MCLK mode is configured, by writing to the
Mode Control 2 register at address 0x05.
● Power up the internal modules of the codec by writing to the Power Management 1
register at address 0x00.
● To set the PLL mode, write to the Power Management 2 register at address 0x01.
● Supply the main clock to the codec (either the MCLK or the SCK/WS clocks) by
sending dummy data (this clock must be supplied through all subsequent operations).
● Choose the audio output device:
– select headphone by writing to the Mode Control 4 register at address 0x0F
– select speaker by writing to the Signal Select register at address 0x02
● Configure the digital volume by writing to the Lch Digital Volume Control and Rch
Digital Volume Control registers at addresses 0x0A and 0x0D, respectively.
● Power up:
– the speaker by writing to the Power Management 1 register at address 0x00
– the headphone by writing to the Power Management 2 register at address 0x01
● Exit the Mute mode by writing to the Power Management 1 register at address 0x00.
● Send the audio data through the I
2
S interface and stop I
2
C communications.
In the I2S_CODEC driver file, a single function performs the codec configuration:
CODEC_Config(u16 OutputDevice, u16 I2S_Standard, u16 I2S_MCLKOutput, u8 Volume)
2.2.2 STM32F103xx and board configuration
The STM32F103xx peripherals used for this application are: I2S2 for audio communication,
I2C1 for codec configuration and the memory interface (could be FSMC for NOR Flash
memory or SPI1 for SPI_Flash memory, etc.).
● Since the MCLK feature is enabled, configure MCKI Jumper (JP18) in the 2<>3
position to connect the I2S2 MCLK signal to the MCLKI codec pin.
● If the audio file to be played has a big size, it should be previously loaded into the
memory source (NOR Flash memory or SPI Flash) using an independent application
(IAP, DFU, etc.). It may also be included as a table file.

ST STM32F103 series Specifications

General

Brand	ST
Model	STM32F103 series
Category	Microcontrollers
Language	English