AN2739 I
2
S general description
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To decide if MCLK should be generated or not, the following facts have to be taken into
consideration:
● The external I
2
S device requirements (codec/DAC).
In general these devices need a master clock (usually at the rate 256 × F
S
) to perform
internal and sampling operations.
● The audio frequency accuracy is, in some cases, compromised by enabling the MCLK
output (that is when a low-frequency clock is driving the STM32F103xx system
(SYSCLK less than 36 MHz)).
The audio communication can be controlled in one of the following ways:
– by polling on the TXE/RXNE flag (bits 1/0 in SPI_CR2 register): wait until
TXE/RXNE flag is set then write/read the channel wave data to/from the SPI_DR
register. (Suitable for tests/small applications, etc.)
– Interrupt on TXE/RXNE: configure and enable the transmit/receive interrupt. And
in the interrupt subroutine, write/read the channel wave data to/from the SPI_DR
register. (Suitable for most applications/RT software, etc.)
– DMA transfer: configure the DMA to load/unload the data from/to the SPI_DR
register on each Rx/Tx request. (Suitable for high-performance requirements.)
Note: In I
2
S mode, the DMA is used in exactly the same way as the SPI mode (with respect to the
supported audio transmission protocols, the CRC feature is not available in I
2
S mode).
The choice of the SYSCLK frequency directly impacts the I
2
S transmission quality (in
master mode): the sampling clock (CK) and WS clock are derived directly from SYSCLK
divided by a 9-bit prescaler in order to obtain the most accurate F
S
frequency. For maximum
accuracy, the prescaler allows odd division by two (using the ODD bit in the SPI_I2SPR
register).
But when the SYSCLK frequency is too low (it is typically greater than 36 MHz), the division
results in a low accuracy factor leading to audio quality degradation.
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