15
PCI/PCIO
The PCI/PCIO diagnostic performs the following:
a. vendor_ID_test – Verifies the PCIO ASIC vender ID is 108e.
b. device_ID_test – Verifies the PCIO ASIC device ID is 1000.
c. mixmode_read – Verifies the PCI configuration space is accessible as
half-word bytes by reading the EBus2 vender ID address.
d. e2_class_test – Verifies the address class code. Address class codes include
bridge device (0 x B, 0 x 6), other bridge device (0 x A and 0 x 80), and
programmable interface (0 x 9 and 0 x 0).
e. status_reg_walk1 – Performs walk-one test on status register with mask
0 x 280 (PCIO ASIC is accepting fast back-to-back transactions, DEVSEL timing
is 0 x 1).
f. line_size_walk1 – Performs tests a through e.
g. latency_walk1 – Performs walk one test on latency timer.
h. line_walk1 – Performs walk one test on interrupt line.
i. pin_test – Verifies interrupt pin is logic-level high (1) after reset.
CODE EXAMPLE 3 identifies the PCI/PCIO output message.
CODE EXAMPLE 3 PCI/PCIO Output Message
Enter (0-12 tests, 13 -Quit, 14 -Menu) ===> 0
TEST='all_pci/PCIO_test'
SUBTEST='vendor_id_test'
SUBTEST='device_id_test'
SUBTEST='mixmode_read'
SUBTEST='e2_class_test'
SUBTEST='status_reg_walk1'
SUBTEST='line_size_walk1'
SUBTEST='latency_walk1'
SUBTEST='line_walk1'
SUBTEST='pin_test'
Enter (0-12 tests, 13 -Quit, 14 -Menu) ===>
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