Supermicro H13SSL-N - Chipset Block Diagram

15
Chapter 1: Introduction
Figure 1-4. System Block Diagram
Chipset Block Diagram
Note: This is a general block diagram and may not exactly represent the features on your
motherboard. See the previous pages for the actual specications of your motherboard.
5 4 3 2 1
C
B
ID LEDID SW
SATA12
CPU SATA[14:15]
SATA13
SATA15
SATA14
CPU SATA[16:17]
USB 3.0
X 2
Rear I/O
LAN1
+
USB3.0 X 2 LAN2
USB3.0 X 2
VGA
MLAN
H13SSL-N/NT
JMCIO3
AMD SP5 Rev. 1.01
USB 3.0
X 2
M.2-H1
M.2 Conn
M key
M.2-H2
CPU G3 [3:0]
SATA[23:20]
M.2 Conn
M key
CPU G3 [7:4]
SATA[27:24]
UPD720202
USB controller
J1
G2
P1
SLOT3
PCIe x16
CPU P4 [0]
DDR5 DIMM
CPU
DDR5 DIMM
BMC ROM
SPI0
J9
BIOS ROM
JMCIO2
#0
SLOT1
PCIe x16
CPU SATA[11]
J15
TPM
BMC
AST2600
JMCIO1
CPU G1 [15:8]
J
CPU SATA[10]
SPI
C
SATA [00:07]
USB2.0 [3:2]
#0
DDR5 DIMM
CPU SATA[12]
EMMC
DDR5 DIMM
J5
H
J2
DDR5 DIMM
SATA8
J12
US3.0 [1:0] / USB2.0 [1:0]
DDR5 DIMM
10Gb LAN
RJ45
J8
J18
DDR5 DIMM
CPU SATA[13]
DDR5 DIMM
K
J4
DDR5 DIMM
P0
J3
#0
P3
SATA9
A
#0
J7
SLOT2
PCIe x8
CPU G1 [7:0]
CPU P5 [0]
D
SLOT5
PCIe x16
E
#0
G1
CPU G0 [0:3]
DDR4
#0 #0
DDR5 DIMM
SATA11
CPU P1 [8:15]
J16
#0
BCM57416
(co-lay BCM5720L)
P4
ESPI1
J11
#0
SLOT4
PCIe x8
G0
J10
CPU P5 [2]
#0
EPYC Processor (AMD Socket SP5)
EMMC
UPD720202
USB controller
#0
G
P2
P5
L
MCIO
x8
DDR5 DIMM
SATA10
IPMI LAN
RJ45
J13
JUSB1
EMMC
SPI
B
MCIO
x8
DDR5 DIMM
COM1
#0
CPU P3 [0:15]
CPU P2 [15:0]
G3
CPU P1 [0:7]
J14
F
PHY
RTL8211F
I
CPLD
J17
VGA
CPU G2 [15:0]
10Gb LAN
RJ45
J6
USB 3.0
X 2
ESPI0
MCIO
x8
CPU P0 PCIe [0:7]