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Supermicro X12DPi-N6 - Page 86

Supermicro X12DPi-N6
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Super X12DPi-N6/X12DPi-NT6 User's Manual
86
CPU1 Core Disable Bitmap/CPU2 Core Disable Bitmap
The following features will display:
Available Bitmap: The available Bitmap will displayed.
Core Disable Bitmap (Hex)
Enter 0 to enable all CPU cores. Enter FFFFFFFFFFF to disable all CPU cores. Please
note that at least one core per CPU must be enabled. Disabling all cores is not allowed.
The default option is 0.
Hyper-Threading (ALL)
Select Enable to use Intel Hyper-Threading Technology to enhance CPU performance. The
options are Enable and Disable.
Hardware Prefetcher
If this feature is set to Enable, the hardware prefetcher will prefectch data from the main
system memory to Level 2 cache to help expedite data transmission to enhance memory
performance. The options are Disable and Enable.
Adjacent Cache Prefetch
Select Enable for the CPU to prefetch both cache lines for 128 bytes as comprised. Select
Disable for the CPU to prefetch both cache lines for 64 bytes. The options are Disable and
Enable. (Note: Refer to Intel’s website for detailed information.)
DCU Streamer Prefetcher
If this feature is set to Enable, the DCU (Data Cache Unit) streamer prefetcher will prefetch
data streams from the cache memory to the DCU (Data Cache Unit) to speed up data
accessing and processing to enhance CPU performance. The options are Disable and Enable.
DCU IP Prefetcher
This feature allows the system to use the sequential load history, which is based on the
instruction pointer of previous loads, to determine whether the system should prefetch
additional lines. The options are Enable and Disable.
LLC Prefetch
If this feature is set to Enable, LLC (hardware cache) prefetching on all threads will be
supported. The options are Enable and Disable.
Extended APIC (Extended Advanced Programmable Interrupt Controller)
Based on the Intel Hyper-Threading technology, each logical processor (thread) is assigned
256 APIC IDs (APIDs) in 8-bit bandwidth. When this feature is set to Enable, the APIC ID will
be expanded from 8 bits to 16 bits to provide 512 APIDs to each thread for CPU performance
enhancement. The options are Disable and Enable.

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